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485 Views
Registered: ‎10-08-2019

Each VCCINT power pin supplies which portion?

Hello Everyone,

I would like to design a PCB to see whether it is possible to connect the FPGA power pins across different power planes (most PCB designs draw the current from the same source). This is a research procedure to see how the FPGA fabric would react to such circumstances.

I could see many VCCINT power pins at the backside supplying the internal configurable resources. However, I did not find any explicit description in Xilinx documents regarding, e.g., VCCINT1 pin is supporting CLBX0Y0~CLBX10Y10.

So, I would like to figure out whether an individual VCCINT power pin control a pre-defined region or all of the pins jointly work for the entire FPGA fabric.

Thank you!

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8 Replies
seamusbleu
Voyager
Voyager
460 Views
Registered: ‎08-12-2008

In general, VCCINT covers the entire chip (I left myself on out, I don't remember if there is any separation on VCCINT on parts that have multiple silicon regions or not), but VCCO covers an individual bank for use in the bank's I/O.   See device diagram figures in UG575 to give you an idea how that breaks down.  Below is an example, with different colors representing banks that can have different voltages (note that I'm glossing over details especially related to the GT banks).  But it never gets down to the individual pin, let alone to different CLB's.  

seamusbleu_0-1630607606146.png

 

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avrumw
Expert
Expert
444 Views
Registered: ‎01-23-2009

I don't think you will get a solid answer from Xilinx on this (I don't think this is published material), but...

In most ASICs (and an FPGA is just an ASIC) a single power domain (in this case VCCINT) is global; the entire chip is powered by the same internal power distribution network (usually a mesh that traverses the entire chip). So while there are multiple VCCINT pins, there is only one internal VCCINT in the FPGA.

So why have multiple VCCINT pins?

The answer is a combination of things:

  • Current handling
    • One pin between the PCB and the internal power grid wouldn't be able to handle the current required
    • Putting N pins in parallel splits the current on any one (roughly) by a factor of N
  • Inductance
    • Each power pin has an inherent inductance. This means that it is slow to respond to changes in current. The further the current spike is from the power pin, the longer it will take the power grid to recover (this is called power supply droop)
    • Having multiple pins scattered around the internal grid
      • shortens the path to the nearest pin (shortening the droop) and
      • reduces the overall inductance (inductors in parallel reduce overall inductance)
  • Probably a few other more esoteric analog reasons

So, back to your question... On a conventional FPGA (a monolithic die - not a stacked silicon interconnect) I am pretty sure all VCCINTs are connected together. On an FPGA with stacked silicon interconnect (a multi-die FPGA with different SLRs), each SLR will have is own power grid. However, I don't know if the silicon interposer connects all these grids together or there are different VCCINT pins for each SLR that are physically separate. This information may be in a Xilinx patent somewhere, but is probably irrelevant - even if these are separate, you would still only get (I think) 4 separate power groups in the largest (and hideously expensive) FPGAs.

Avrum

joancab
Teacher
Teacher
430 Views
Registered: ‎05-11-2015

As perfectly explained, it's all one supply domain and all supply pins are connected together to the same rail, so the logical layout is having one VCCINT plane for all those pins.

You can still split the VCCINT pins and use different planes for each set, but they will be internally connected so the source needs to be the same or compatible with shorting together.

 

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303 Views
Registered: ‎10-08-2019

Thanks for the detailed reply.

I am more interested in VCCO right now given the VCCINT pins are essentially connected together. Would you please further explain "But it never gets down to the individual pin, let alone to different CLB's"?

Based on my understanding, the VCCO only supplies the input/output buffers. Will they impact the CLBs as well?

What I am trying to do is to implement some on-chip power-aware primitives (e.g., ring oscillator) to see whether we are able to sense the different power rails on the same FPGA silicon. Is this possible in your mind? Thank you.

 

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300 Views
Registered: ‎10-08-2019

Thanks a lot for the explanation. Per the comment above, VCCO pins are separated in terms of IO banks. I would like to explore how to use this to implement my potential research idea.

What I am trying to do is to implement some on-chip power-aware primitives (e.g., ring oscillators) to see whether we are able to sense the different power rails on the same FPGA silicon. Is this possible in your mind? Thank you.

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300 Views
Registered: ‎10-08-2019

Thanks a lot for the explanation. Per the comment above, VCCO pins are separated in terms of IO banks. I would like to explore how to use this to implement my potential research idea.

What I am trying to do is to implement some on-chip power-aware primitives (e.g., ring oscillators) to see whether we are able to sense the different power rails on the same FPGA silicon. Is this possible in your mind? Thank you.

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joancab
Teacher
Teacher
277 Views
Registered: ‎05-11-2015

There is probably just one power domain in Xilinx FPGAs. Even if there were more than one, details are not public and I don't think Xilinx would share them with you or me.

But I don't want to discourage you. Try empirically: 

- Power the FPGA with one supply pin (current will be very limited)

- Have different designs with logic in different areas

- Find which ones work (powered) and which don't (unpowered)

- Repeat until all areas and all pins have been explored

Enjoy that (in my opinion) waste of time.

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bpatil
Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎03-07-2018

Hi zht247200@gmail.com 

I believe Table 1-3: FPGA Resources and their Power Supply provided in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug440-xilinx-power-estimator.pdf will be helpful for you.

Regards,
Bhushan

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