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Visitor odedyer
Visitor
4,163 Views
Registered: ‎09-04-2016

Elaborated report of LUTs used in the design

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Hi,

 

What is the most elaborated report I can get on the LUTs used in a part of my design?

Among the rest, I want to get a count of the LUTs in use by number of inputs (i.e how many LUTs have 2, 3, 4, 5 or 6 inputs in use).

In the utilization report, I can only see a breakdown by the outputs in use (O5 only, O6 only, O5 and O6).

 

In addition, I'm having difficulties understanding the report. As can be seen below, the instance "inst" has less LUTs than "pixel_dist_st", even though it includes it. How is this counting explained?utilization

 

Thanks!!

 

Oded

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Xilinx Employee
Xilinx Employee
7,440 Views
Registered: ‎09-05-2007

Re: Elaborated report of LUTs used in the design

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I agree that the device itself has the LUT6_2 so that is what your design actually uses. How well it uses each LUT depends on the design and how a good engineer writes code that results in higher efficiency implementations (e.g. is thoughtful about architecture when writing code).

 

The synthesis report does break down the number of inputs on each LUT that it hands on to the Implementation phase. I think this is probably what you are looking for.

 


7. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE     |  324 |        Flop & Latch |
| LUT6     |  190 |                 LUT |
| LUT5     |  122 |                 LUT |
| RAMD32   |   24 |  Distributed Memory |
| SRL16E   |   16 |  Distributed Memory |
| CARRY4   |   10 |          CarryLogic |
| OBUF     |    9 |                  IO |
| LUT2     |    9 |                 LUT |
| RAMS32   |    8 |  Distributed Memory |
| RAMD64E  |    8 |  Distributed Memory |
| LUT4     |    4 |                 LUT |
| RAMB36E1 |    3 |        Block Memory |
| IBUF     |    2 |                  IO |
| FDSE     |    2 |        Flop & Latch |
| MUXF7    |    1 |               MuxFx |
| LUT3     |    1 |                 LUT |
| IBUFDS   |    1 |                  IO |
| BUFG     |    1 |               Clock |
+----------+------+---------------------+

Ken Chapman
Principal Engineer, Xilinx UK

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4 Replies
Moderator
Moderator
4,152 Views
Registered: ‎11-09-2015

Re: Elaborated report of LUTs used in the design

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Hi @odedyer,

 

What do you mean by " most elaborated report".

 

About the reason why you have only LUT5 and LUT6 in your report is because in the 7series/Ultrascale/Ultrascale+ FPGAs, you have only 6-LUT (which can be used as 2 5-LUT):

LUTs.JPG

From UG474 (link):

LUTs2.JPG

 

If you have a 2/3/4-LUT, it will still use a 5-LUT so O5 or O6 only.

 

About the counting, I don't really know why you have this. Do you have a test case? Which vivado version are you using? If not 2016.4 could you try with it?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
4,139 Views
Registered: ‎08-01-2008

Re: Elaborated report of LUTs used in the design

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You can run "report_utilization" Tcl command to report utilization for a specific module.

Run "report_utilization -help" in Tcl console to see details.
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
7,441 Views
Registered: ‎09-05-2007

Re: Elaborated report of LUTs used in the design

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I agree that the device itself has the LUT6_2 so that is what your design actually uses. How well it uses each LUT depends on the design and how a good engineer writes code that results in higher efficiency implementations (e.g. is thoughtful about architecture when writing code).

 

The synthesis report does break down the number of inputs on each LUT that it hands on to the Implementation phase. I think this is probably what you are looking for.

 


7. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE     |  324 |        Flop & Latch |
| LUT6     |  190 |                 LUT |
| LUT5     |  122 |                 LUT |
| RAMD32   |   24 |  Distributed Memory |
| SRL16E   |   16 |  Distributed Memory |
| CARRY4   |   10 |          CarryLogic |
| OBUF     |    9 |                  IO |
| LUT2     |    9 |                 LUT |
| RAMS32   |    8 |  Distributed Memory |
| RAMD64E  |    8 |  Distributed Memory |
| LUT4     |    4 |                 LUT |
| RAMB36E1 |    3 |        Block Memory |
| IBUF     |    2 |                  IO |
| FDSE     |    2 |        Flop & Latch |
| MUXF7    |    1 |               MuxFx |
| LUT3     |    1 |                 LUT |
| IBUFDS   |    1 |                  IO |
| BUFG     |    1 |               Clock |
+----------+------+---------------------+

Ken Chapman
Principal Engineer, Xilinx UK

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Visitor odedyer
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4,115 Views
Registered: ‎09-04-2016

Re: Elaborated report of LUTs used in the design

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Thanks!

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