09-02-2015 12:25 PM
Please forgive me -- I am a FPGA newbie, have A LOT of questions. Here come the first 2:
1. I managed to re-build and load the example IBERT design for bank 213, but cannot seem
to be able to change the bit rate from 6.25 G to 2.5 G. I could re-config the GTP, the project
could build, but when I load the new bit file, the link status still says 6.25 Gbps. What am I
2. What I really need is an example design to use the SFP (with GTP x0y0). I need to use 8p/10p
to test some communication.
Thank you very much in advance,
(I use Vivado 2015.2)
09-02-2015 01:33 PM
Thank you very much for helping!
I was referring to the "Status" inside the "Serial I/O Links" panel on the bottom of Vivado.
Could you point me to an example GTP design for the SFP on AC701? Sorry if it too simple,
I just cannot find anybody talking about it anywhere.
09-02-2015 09:09 PM
have you tried to run the example design available at this link
09-04-2015 09:08 AM
Thank you very much for helping.
Yes, I could re-build and run the IBERT example project. One confusion is that I tried
to change the rate from 6.25 to 2.5. The IP was configured, the project could build. But
when I load it, the "Serial I/O Links" still shows "6.250 Gbps".
And, which ports are the "RX PLL Status" and "TX PLL Status"? When I remove the
loopback fiber, they still show "Locked".
Which output port showes that the RX CDR is locked? Is it "RXCDRLOCK"? I am looking
for an indicator to show that the RX is getting data from the fiber. So when the fiber is
unplugged, it provides a warning.
09-06-2016 07:02 AM
09-08-2016 10:58 AM - edited 09-08-2016 10:59 AM
I tried to change the rate from 6.25 to 2.5.
How did you do it? Is it from core generation GUI?