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dhzhang
Newbie
Newbie
6,023 Views
Registered: ‎09-02-2015

Example design for AC701 SFP

Hi,

 

Please forgive me -- I am a FPGA newbie, have A LOT of questions. Here come the first 2:

 

1. I managed to re-build and load the example IBERT design for bank 213, but cannot seem

     to be able to change the bit rate from 6.25 G to 2.5 G.  I could re-config the GTP, the project

     could build, but when I load the new bit file, the link status still says 6.25 Gbps.  What am I

     missing?

 

2. What I really need is an example design to use the SFP (with GTP x0y0).  I need to use 8p/10p

    to test some communication.

 

Please help!

 

Thank you very much in advance,

(I use Vivado 2015.2)

 

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6 Replies
austin
Scholar
Scholar
6,014 Views
Registered: ‎02-27-2008

d,

 

What "link status"?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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fpgaioc
Observer
Observer
6,010 Views
Registered: ‎09-02-2015

Hi Austin,

 

Thank you very much for helping!

 

I was referring to the "Status" inside the "Serial I/O Links" panel on the bottom of Vivado.

 

Could you point me to an example GTP design for the SFP on AC701?  Sorry if it too simple,

I just cannot find anybody talking about it anywhere.

 

Best regards,

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htsvn
Xilinx Employee
Xilinx Employee
5,977 Views
Registered: ‎08-02-2007

hi,

 

have you tried to run the example design available at this link

 

--hs

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fpgaioc
Observer
Observer
5,963 Views
Registered: ‎09-02-2015

Hi HS,

 

Thank you very much for helping.

 

Yes, I could re-build and run the IBERT example project.  One confusion is that I tried

to change the rate from 6.25 to 2.5.  The IP was configured, the project could build.  But

when I load it, the "Serial I/O Links" still shows "6.250 Gbps".

 

And, which ports are the "RX PLL Status" and "TX PLL Status"?  When I remove the

loopback fiber, they still show "Locked".

 

Which output port showes that the RX CDR is locked?  Is it "RXCDRLOCK"?  I am looking

for an indicator to show that the RX is getting data from the fiber.  So when the fiber is

unplugged, it provides a warning.

 

Best regards,

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balkris
Xilinx Employee
Xilinx Employee
3,223 Views
Registered: ‎08-01-2008

https://forums.xilinx.com/t5/7-Series-FPGAs/Example-design-for-AC701-SFP/td-p/652571

http://www.xilinx.com/support/documentation/boards_and_kits/ac701/2014_3/xtp224-ac701-ibert-c-2014-3.pdf

http://www.xilinx.com/support/documentation/boards_and_kits/ac701/2014_3/xtp224-ac701-ibert-c-2014-3.pdf
Thanks and Regards
Balkrishan
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venkata
Moderator
Moderator
3,200 Views
Registered: ‎02-16-2010

I tried to change the rate from 6.25 to 2.5.

How did you do it? Is it from core generation GUI?

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