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642 Views
Registered: ‎01-06-2020

Example using the XRFSoC Data Converter

Hello,

 

I'm trying to get the loopback working on a ZCU111 with the  XBM500, I have two sma connected with P/N crossed however I don't seem to find an example to use Vitis with standalone to program and send receive from ADC to ADC on C.

 

I have it all build, but I can't find an example on how to leverage the standalone format and make an application to read/write the ADC/DAC units on the board, like how o initially setup and etc, there are some examples using a a closed app from some example, but no example on how I can use and access the devices on my own.

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617 Views
Registered: ‎01-06-2020

basically in the latest 2020.2  zcu111_MTSDesign_8x8 from rdf0476 what is the ADC Data Capture block and DAC Stimuylus Block? and how toa access them then?

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pthakare
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593 Views
Registered: ‎08-08-2017

Hi @muscularbeaverwhoosh 

Chapter 6 (Example Design) in IP product guide below  has covered this blocks

https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_4/pg269-rf-data-converter.pdf

Do you want external loopback  DAC -> ADC or Internal loopback ADC -> DAC ?

The example applications code provided below works with example design 

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/rfdc/examples

The example design is created using right click to IP -> Open example design 

 

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579 Views
Registered: ‎01-06-2020

Thanks, but the example has an RTL block reading and writing, through the AXI Stream. Regarding the 2020.2 MTS_8x8 examples, that is a more "high/intensive data volume", in that case, I assume the process goes through the AxiDMA, like in the AxiDMA examples. Am I correct until here? Took me a whole day to figure because there is no example in using the A53, to send receive data on standalone/baremetal.

I have a current Design where I have all AXIS  and MAXIS of the DataConveter connected into a few peripheral interconnect, and there are a few issues with the timing of that. I create a derivative design, using DMA in and A DMA out, however, I didn't add the DDR4, and the DMA is before a peripheral interconnect and after, I don't particularly like it, but solve the timing issue, since I can make it work, however after exporting it the XRFSoC drivers where not present when I created the platform, so I can't access the unit 

muscularbeaverwhoosh_0-1621915569478.png

 

muscularbeaverwhoosh_1-1621915605338.pngmuscularbeaverwhoosh_2-1621915631425.png

 

muscularbeaverwhoosh_3-1621915665434.pngmuscularbeaverwhoosh_4-1621915696110.png

 

To be clear in my intent: is to use all DAC and ADC, in parallel, control by the MPSoC directly or indirectly, Yes like in the example I can create a secondary block to interface with ARM, and use this block to feed the DAC and another to sample the ADC, and feed the ARM.

Currently, I'm trying to get the loopback working ASAP, so then I can refine it and add more modules, and figure it out the best RTL design to extract the most performance of it. 

 

 

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pthakare
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555 Views
Registered: ‎08-08-2017

Hi @muscularbeaverwhoosh 

The designs provided in package (like MTS ,NON-MTS , SSRIP) are to be used with ZCU111 Evaluation GUI.

The documentation around this is 

https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/2020_2/ug1287-zcu111-rfsoc-eval-tool.pdf

https://www.xilinx.com/support/documentation/user_guides/ug1309-rf-data-converter-interface.pdf

Now coming to your requirement ,

We do have some starter designs hosted under lounge and you need to request for access. 

Are you in contact with FAE  (Form Avnet or Xilinx) who can assist on getting the access to lounge?

 

 

 

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498 Views
Registered: ‎01-06-2020

thanks, @pthakare, not an FAE, only direct support inside Xilinx (not sure if is not you) by email, with an open case.

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462 Views
Registered: ‎01-06-2020

How can I get those LOUNGE designs you mentioned?

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pthakare
Moderator
Moderator
435 Views
Registered: ‎08-08-2017

Hi @muscularbeaverwhoosh 

There is link to request the access.

Can you provide me the case (SR) number ? 

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402 Views
Registered: ‎01-06-2020

SR# 10516141

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pthakare
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355 Views
Registered: ‎08-08-2017

Hi @muscularbeaverwhoosh 

Thanks , i checked it and this one is owned by timing expert . I will try to share the link with him to send on SR email thread.

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297 Views
Registered: ‎01-06-2020

Got it, our discussion is more architectural here, I think are two parallel discussions.

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