05-24-2021 02:37 PM
I'm trying to get the loopback working on a ZCU111 with the XBM500, I have two sma connected with P/N crossed however I don't seem to find an example to use Vitis with standalone to program and send receive from ADC to ADC on C.
I have it all build, but I can't find an example on how to leverage the standalone format and make an application to read/write the ADC/DAC units on the board, like how o initially setup and etc, there are some examples using a a closed app from some example, but no example on how I can use and access the devices on my own.
05-24-2021 04:21 PM
basically in the latest 2020.2 zcu111_MTSDesign_8x8 from rdf0476 what is the ADC Data Capture block and DAC Stimuylus Block? and how toa access them then?
05-24-2021 08:04 PM
Chapter 6 (Example Design) in IP product guide below has covered this blocks
Do you want external loopback DAC -> ADC or Internal loopback ADC -> DAC ?
The example applications code provided below works with example design
The example design is created using right click to IP -> Open example design
05-24-2021 09:08 PM - edited 05-24-2021 09:11 PM
Thanks, but the example has an RTL block reading and writing, through the AXI Stream. Regarding the 2020.2 MTS_8x8 examples, that is a more "high/intensive data volume", in that case, I assume the process goes through the AxiDMA, like in the AxiDMA examples. Am I correct until here? Took me a whole day to figure because there is no example in using the A53, to send receive data on standalone/baremetal.
I have a current Design where I have all AXIS and MAXIS of the DataConveter connected into a few peripheral interconnect, and there are a few issues with the timing of that. I create a derivative design, using DMA in and A DMA out, however, I didn't add the DDR4, and the DMA is before a peripheral interconnect and after, I don't particularly like it, but solve the timing issue, since I can make it work, however after exporting it the XRFSoC drivers where not present when I created the platform, so I can't access the unit
To be clear in my intent: is to use all DAC and ADC, in parallel, control by the MPSoC directly or indirectly, Yes like in the example I can create a secondary block to interface with ARM, and use this block to feed the DAC and another to sample the ADC, and feed the ARM.
Currently, I'm trying to get the loopback working ASAP, so then I can refine it and add more modules, and figure it out the best RTL design to extract the most performance of it.
05-24-2021 10:59 PM
The designs provided in package (like MTS ,NON-MTS , SSRIP) are to be used with ZCU111 Evaluation GUI.
The documentation around this is
Now coming to your requirement ,
We do have some starter designs hosted under lounge and you need to request for access.
Are you in contact with FAE (Form Avnet or Xilinx) who can assist on getting the access to lounge?
05-25-2021 10:43 AM - edited 05-25-2021 10:43 AM
05-25-2021 07:42 PM
There is link to request the access.
Can you provide me the case (SR) number ?
05-26-2021 08:29 PM
Thanks , i checked it and this one is owned by timing expert . I will try to share the link with him to send on SR email thread.