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407 Views
Registered: ‎12-06-2018

FMC I/O Nexys Video Artix 7

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Hi

I have a question regarding the input/output of the FMC connector on the nexys video evaluation board. As far as I can tell it contains an Artix-7 FPGA.
I want to use the I/O's for LVDS signals.It seams like the I/O is powered by the V_adj which can be set to different voltage levels.

1) Is it possible to select different voltage levels for different output pairs or will all outputs have the same voltage level? I want 1.8 V differential signals and 1.2 V LVDS signals.

2) Can I configure the differential clock pair as LVDS?

3) Can I choose some pairs to be differential and some pairs to be 2 single ended signals, or do I all pairs have to be the same type?

Regards
Michelle

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Contributor
Contributor
377 Views
Registered: ‎04-27-2016

Re: FMC I/O Nexys Video Artix 7

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1) Is it possible to select different voltage levels for different output pairs or will all outputs have the same voltage level? I want 1.8 V differential signals and 1.2 V LVDS signals.

All I/Os of the FMC connector are routed to bank 15 and bank 16 which are powered by V_ADJ. You can set V_ADJ to 1.2 V (default), 1.8 V, 2.5 V, or 3.3 V. The used IO standard of your FPGA pin must be compatible with that voltage. That means for example you can use LVDS IO standard with V_ADJ at 1.8 V. You can't mix it all. LVDS output with bank voltage != 1.8 V is not supported (LVDS Interface checklist https://www.xilinx.com/support/answers/43989.html)

2) Can I configure the differential clock pair as LVDS?

I don't know exactly which clock pair you mean, but in general you can do this.

3) Can I choose some pairs to be differential and some pairs to be 2 single ended signals, or do I all pairs have to be the same type?

Yes this is no problem. But used IO standards must be compatible with your bank voltage (V_ADJ). E.g. LVCMOS18 (single ended signals) and LVDS (differential pairs). Single ended clock inputs should be connected to the positive terminal of an IO pair.

1 Reply
Contributor
Contributor
378 Views
Registered: ‎04-27-2016

Re: FMC I/O Nexys Video Artix 7

Jump to solution

1) Is it possible to select different voltage levels for different output pairs or will all outputs have the same voltage level? I want 1.8 V differential signals and 1.2 V LVDS signals.

All I/Os of the FMC connector are routed to bank 15 and bank 16 which are powered by V_ADJ. You can set V_ADJ to 1.2 V (default), 1.8 V, 2.5 V, or 3.3 V. The used IO standard of your FPGA pin must be compatible with that voltage. That means for example you can use LVDS IO standard with V_ADJ at 1.8 V. You can't mix it all. LVDS output with bank voltage != 1.8 V is not supported (LVDS Interface checklist https://www.xilinx.com/support/answers/43989.html)

2) Can I configure the differential clock pair as LVDS?

I don't know exactly which clock pair you mean, but in general you can do this.

3) Can I choose some pairs to be differential and some pairs to be 2 single ended signals, or do I all pairs have to be the same type?

Yes this is no problem. But used IO standards must be compatible with your bank voltage (V_ADJ). E.g. LVCMOS18 (single ended signals) and LVDS (differential pairs). Single ended clock inputs should be connected to the positive terminal of an IO pair.