FPGA Internal Diode Protection

[jpilkey]

I am trying to evaluate the use of an ESD TVS diode for a PS_MIO pin on the XC7Z020-L1CLG484I FPGA. From the Device Reliability Report (March 22, 2019), I found that the FPGA is rated for 1 kV HBM. From the FPGA data sheet, the maximum input voltage on the MIO pin is a diode drop (0.55 V) from the voltage rails. I'd like to understand the internal FPGA diode characerstics, aside from its presumed 0.55 V forward voltage drop, so that I can properly coordinate external ESD protection.

[drjohnsmith]

You need to get into the world of simulation,
The way is to generate the IBIS model for the pin type you want to use.

For what its worth, ESD is in reality world of guess work,

for instance , if the voltage rails and a pin are all struck by a 1 Kv spike, is that OK then ?
Maybe, but, was it really instantaneous or was it a few ns apart.

In my experience, you are never going to get a company to say, put this on the board and it will pass !!

Dont know what your background is, but this might help

https://www.onsemi.com/pub/Collateral/TND410-D.PDF

https://www.xilinx.com/support/answers/3982.html

https://www.xilinx.com/support/documentation/white_papers/wp433-Mitigating-ESD-EOS.pdf