09-10-2019 02:32 PM
I am trying to evaluate the use of an ESD TVS diode for a PS_MIO pin on the XC7Z020-L1CLG484I FPGA. From the Device Reliability Report (March 22, 2019), I found that the FPGA is rated for 1 kV HBM. From the FPGA data sheet, the maximum input voltage on the MIO pin is a diode drop (0.55 V) from the voltage rails. I'd like to understand the internal FPGA diode characerstics, aside from its presumed 0.55 V forward voltage drop, so that I can properly coordinate external ESD protection.
09-10-2019 02:46 PM