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2,633 Views
Registered: ‎01-22-2015

FPGA creates main clock for ADC

I’ve inherited a board where the FPGA (Kintex-7) creates the main clock (CLKP+CLKM) for an ADC (TI ADS62P24).  In <this post> Avrum explains why this is a bad idea.  So, I’m wondering how to make the best of this bad situation.

 

What architecture inside the FPGA should be used to create the ADC main clock – which is currently sent to the ADC via standard I/O pins (LVDS)?

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Explorer
Explorer
2,593 Views
Registered: ‎05-08-2018

Re: FPGA creates main clock for ADC

Mark,

 

Use the PLL in the CMT  (not the MMCM), with a BUFG to a clock forwarding DDR DFF's in the IOB for the LVDS clock output.

 

Keep and single-ended inputs and outputs from the IO bank used for clock forwarding. If not possible, keep them from the adjacent pins.  Use virtual grounds if possible to isolate the DDR clock output.

 

If the same clock is used elsewhere, use the 270 degree phase shifted version internally.

 

Best you can get is ~ 100ps p-p jitter using the above. Hopefully that amount of jitter will not degrade the effective number of bits (resolution).

 

Austin

Scholar drjohnsmith
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2,589 Views
Registered: ‎07-09-2009

Re: FPGA creates main clock for ADC

How many bits do you want, at what sample rate, and whats your input signal bandwidth

 

The clock jitter adds noise to the adc, which limits the Effective Number Of Bits , for any one sample.

 

see fig 3 here

http://www.analog.com/en/analog-dialogue/articles/analog-to-digital-converter-clock-optimization.html

 

Once you know the effect the jitter you have is having on your ENOB, you can decide what you can do.

 

One option is to lower the bandwidth of the input signal and / or over sample and average / filter the adc output.

     

the other is to try to de jitter the sample clock,

    If I remember this ADC, it uses a sample pulse, not a clock, so you can't band pass filter exetrnaly

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Historian
Historian
2,574 Views
Registered: ‎01-23-2009

Re: FPGA creates main clock for ADC

Use the PLL in the CMT  (not the MMCM), with a BUFG to a clock forwarding DDR DFF's in the IOB for the LVDS clock output.

 

While I can't be certain, I would expect that a BUFG is not the best buffer to use - it's probably the worst. The global clock tree runs right through the center (hence noisiest) part of the FPGA and has the longest possible travel from a CMT to an IOB (from the clock column, which is right beside the I/O column, to the BUFGs, which are in the center, then back to the I/O column).

 

I would expect a BUFH to be better than a BUFG (since it doesn't go onto the vertical clock spine, but still goes to the center of the die).

 

I would expect a BUFR to be better than a BUFG or a BUFH since it doesn't need to travel to the center of the die. To get to the BUFR (and the BUFIO) you have to use the first four outputs of the MMCM (The PLL can't reach them - see UG472 "High Performance Clocks"). While it is true that the PLL has better jitter characteristics, the advantage of using the high performance clocks may make this a better solution than using the PLL.

 

I would expect a BUFIO (again via the High Performance Clocks) to be the best solution of all. But, of course, you can't clock any internal logic with this clock...

 

Some of the other things mentioned by @alesea are good recommendations though... Try to keep this clock away from other noisy stuff, both physically (don't put high drive I/O beside the I/O driving the clock) and temporally (try to keep the edges of this clock away from the edges of other clocks - use different phases of the clock if necessary).

 

Avrum

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Registered: ‎05-08-2018

Re: FPGA creates main clock for ADC

Avrum,

 

BUFG v BUFR v other global clock resource is likely all equal as they have all the same layouts, buffering, shielding.

 

If anyone has seen a difference, that would be interesting to know.

 

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2,527 Views
Registered: ‎01-22-2015

Re: FPGA creates main clock for ADC

I’m very grateful for comments from each of you.

 

I’ll investigate the level of jitter I can tolerate, attempt to test architectures you have proposed, and post result here.

 

-very glad you’re still with us, Austin!

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Historian
Historian
2,509 Views
Registered: ‎01-23-2009

Re: FPGA creates main clock for ADC

If you are actually going to try and do jitter measurements, you need to ensure that your FPGA usage is typical. The jitter degradation in an otherwise empty FPGA will be very small as compared to and FPGA that is doing things. The concern with the global clocks is how much distance the clock network spends near other active circuitry which is inducing noise onto the clock line. If the FPGA (and particularly the other clocks) are essentially idle, then there is no noise to couple in.

 

Only if the FPGA is active in a way that is representative of your final design can you really get meaningful information from these tests...

 

Avrum

2,335 Views
Registered: ‎01-22-2015

Re: FPGA creates main clock for ADC

On this board, I find that the FPGA clock-inputs and the main clock module (MMCM) are in clock region X1Y1 - and the pin that sends the main-clock to the ADC is in FPGA clock region X0Y3.  
kintex7_clock_regions.jpg

Since I am creating a clock (ADC main-clock) that crosses multiple clock regions in the FPGA, are my architecture options now limited to the following?

   MMCM > BUFG > ODDR   

   PLL > BUFG > ODDR

 

How does creating this clock with 270deg phase shift (as proposed by alesea) help reduce jitter?

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2,329 Views
Registered: ‎05-08-2018

Re: FPGA creates main clock for ADC

Mark,

 

The bounce caused by simultaneous switching of internal logic, or output pins rings at the natural frequency of the package LC.  270 degree seems to be a null in the ringing.  Not always true, but it was observed by my team on many boards with system clocks 100 to 200 MHz.  Faster clocks have less ringing, and this trick is not useful.  So, I suggest you scope the Vccint, and sync to the most used clock.  If you see a minimum in Vccint bounce at 270 degrees, then moving a clock to that domain will reduce jitter for that set of registered signals.

 

Austin 

Scholar drjohnsmith
Scholar
2,324 Views
Registered: ‎07-09-2009

Re: FPGA creates main clock for ADC

I'd like to know the answer to , what jitter do you need to meet the SNR you need..

 

That is a pure theoretical number / limit

 

Would be good to know,

 

a) Whats the sampling rate

b) Whats the input signal low frequency to high frequency ( bandwidth )

c) How many bits is the ADC 

 

We can then decide what sort of solution you need

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: FPGA creates main clock for ADC

@alesea, what sort of effect would you expect the power to have on the ADC sample clock jitter ?

 

 

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Registered: ‎01-22-2015

Re: FPGA creates main clock for ADC

@alesea– thanks for explanation of 270deg phase shift.   The reason we are fiddling with the main clock of this ADC is that this clock is showing up elsewhere in our system and causing problems.  However, by changing frequency of this clock we can avoid these problems.

 

@drjohnsmith – thanks for being interested in the details and for the reference to Analog Dialog article that you gave previously.   We are trying to use main clock of 60MHz for the ADC which is 12-bit.  Analog input frequency-content ranges from 0-20MHz.  The basic calculation from the Analog Dialog article indicates that we can tolerate 1.5ps RMS jitter for 12bits and 3.2ps RMS jitter for 11 bits.  These numbers equate to about 21ps and 45ps peak-to-peak (p-p) jitter using conversion factor of 14 suggested <here> by Austin.   Given Austin’s estimate above of 100ps p-p for FPGA-generated clock, things seem far out of reach.  Any ideas?

 

 

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: FPGA creates main clock for ADC

Hi

 

For a 20 Mhz analog bandwidth, and 100 ps jitter , your going to get about 6 or 7 bits equivalent ADC. 40 odd db SNR.

 

Is that good enough for you ?

 

Looking at the ADC, your getting 10 or 11 bits at 20 MHz bandwidth anyway,

    And sampling a 20 MHz signal at 60 MHz, you must have a very very good low ripple, high cut off input filter to the ADC.

       If you have not , then the reflected out of band noise is aliasing back down anyway, limiting your SNR more than the jitter.

 

Also remember ,all this only applies for a continuous sampled system,

      If the sampled clock is not continuous, then all calculations are null and void.

 

If the sample clock is constant, and you want to do minimal circuit mods, 

     I'd suggest make the best you can int he fpga, and putting a band filter on the clock ( some L and C ) 

          idealy you want a perfect 60 Mhz clock signal.

      Check but ADC's are very happy ( normally ) with a sine wave clock input ,

          provided is has sufficient amplitude / voltage. Even AC coupled.

            This has by definition, a single frequency, and is low jitter.

 

but again this only works if the clock is constant, 

 

Or you can look at band limiting the input signal to say 5 MHz,

       Again this has to be done in the analog domain,

 

You could also look with the above input filtering, at averaging the samples,

    on assumption noise is gausian, it does not add with averaging, but the signal does,

          every 4 samples you average you gain 6 db.

 

As for generating the best clock from the fpga,

    Use the PLL on chip, 

        clock the ddr output register direct with that is about the best you can do,

 

I must highlight again,

 

if the sampling is not continuous, then all this is null,

    e.g. If you try to grab a sample every second , of a 20 MHz bandwidth limited signal, with 18 bits ADC,

            the sampling theory does not apply,  

 

 

 

 

 

 

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1,843 Views
Registered: ‎01-22-2015

Re: FPGA creates main clock for ADC

@drjohnsmith  - thank you for very thoughtful reply.  You have given me much to think about.  I still hope to do some testing an post results here.

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1,745 Views
Registered: ‎01-22-2015

Re: FPGA creates main clock for ADC

Based on your recommendations, four different methods of generating the ADC main-clock clock have been tested. The relative jitter associated with each method is inferred from measurements of noise, CRMS, on the ADC-reported counts while the ADC is sampling an 11MHz sinewave.  The following table summarizes the test results – and the attached document gives additional details.

results.jpg

 

-again, thanks for your expert guidance. I welcome further comments and suggestions.

 

Mark

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1,739 Views
Registered: ‎05-08-2018

Re: FPGA creates main clock for ADC

Mark,

 

The trick with 270 degrees doesn't do anything, so ringing on Vccint due to SSO internal/external) is not an issue it appears.

 

The PLL filtering also is ineffective.  Adding more global clock resources makes it worse (expected).  At  this point, if you require better EFNOB, it is a relayout to feed a clean clock to the ADC, and also to the FPGA.  Confirms the recommendation to NOT feed the clock through the FPGA device.

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1,728 Views
Registered: ‎01-22-2015

Re: FPGA creates main clock for ADC

Austin,

 

Thanks for your comments.  I am happy with test results since measured ENOB is sufficent for our needs.

 

I just wanted to share test result with you - since I kinda promised I would.

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Explorer
Explorer
1,720 Views
Registered: ‎05-08-2018

Re: FPGA creates main clock for ADC

Mark,

 

Great follow-up.  Appreciated.  The addition of in package decoupling, better clock trees, better board layout suggestions have made the phase shifting trick obsolete.  I suspected that improvements in 7 series and onward were making the trick less useful.  Now we know.

 

Thank you!

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