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Newbie jkopinga
Newbie
396 Views
Registered: ‎02-09-2019

FPGA requirement

Dear Users,

I'm currently using a Spartan-3AN (XC3S200AN) FPGA for generating PWM signals for a Multiphase (15) powersupply for controlling extremely high currents. This device currently runs at 40MHz as the design was migrated from older technology which ran at that speed.

The base frequency of the PWM signals are in the range of 10kHz-40KHz. Now let's assume that we use 10kHz base frequency. Based on the 40MHz clock I can achieve close to 12-bit PWM resolution due to 40MHz / 10kHz = 4000 (Close to 12-bits).

Now the question is....... If in the future I wanted to increase my PWM resolution I'd have to go up with clock speed. I could use the PLL inside the FPGA to go upto 160MHz which would get me close to 14-bits resolution. However I would like to get maybe upto 16-bits resolution if possible (the higher the better).

I'm not exactly sure where the limitations on clock speed are on the Spartan-3AN. Could I do it with the current FPGA or would I need to use something else in order to be able to run those speeds? Like Spartan-6 or Spartan-7?

Looking forward for advice on this as well as to understand actual max. clock frequency from the spec sheet which isn't clear as I see lots of different speeds mentioned for different clocks, etc.

 

Regards,

J.

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4 Replies
382 Views
Registered: ‎09-17-2018

Re: FPGA requirement

j

Code it, constrain it, run it through the tools (ISE 14.7).  If it meets timing, you are  good.  If not, you need a newer device that is faster.  S3 is probably good up to 150 MHz clock without too much difficulty, and with careful coding (pipe lining) 200 MHz is do-able.

l.e.o.

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Scholar u4223374
Scholar
312 Views
Registered: ‎04-26-2015

Re: FPGA requirement

@jkopinga The actual "maximum frequency" for a Spartan 3AN is probably something like 300 - 400MHz. However, getting that will require some extremely careful optimization. Realistically, 100 - 150MHz is likely to be a reasonable target.

 

With the Spartan 3AN, you could potentially use dithering to get a higher effective resolution. If you make every second pulse 1 cycle longer, then you've increased the average pulse length by 0.5 cycles - giving you one bit more resolution. If the output is effectively low-pass filtered (eg. driving a motor, where the momentum neatly filters out these >10kHz deviations in power) then this could work well.

 

With newer chips (eg. Spartan 7) you can use the I/O serializers for much higher resolution, without having to run the fabric faster. I would expect that 16-bit resolution would be quite achievable here.

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Newbie jkopinga
Newbie
284 Views
Registered: ‎02-09-2019

Re: FPGA requirement

Thanks for the information. I'm running a 40MHz external oscillator now. I could use the Clock doubler to try 80MHz first and recode. If that pans out OK I could swap the 40MHz oscillator for a 80MHz one and try 160MHz and see if I can make it work.

I guess that's about as ambitious as I would want to get on the Spartan-3AN. I'll definitely check into the Spartan-7 or Artix-7 series which I like. Also the fact that there is an additional 2x 12-bits ADC there excites me as I could use that to do lots more system checks on the background.

Cheers,

J.

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257 Views
Registered: ‎09-17-2018

Re: FPGA requirement

Does your device have a DCM?  Does it have a DFS?

If so, you can multiply your clock (and divide it as well) to get M/D times your crystal frequency (M=2 to 31, D = 2  to 31).

l.e.o.

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