08-30-2017 08:27 AM
We currently have products that use the XC2V500-4FGG256C and the XC2V1000-4FGG456C, Virtex-II products. Is there a way to get documentation on the dimensions of the FPGAs: length, width, distance between I/Os, and so forth? We will need to update our products and we are looking to do a full update to a much newer product so we will not have to deal with this issue in the near future. We are planning to update to the Spartan-6 product line. XC2V500-4FGG256C to XC6SLX9-2FTG256C and XC2V1000-4FGG456C (171 I/Os utilized) to XC6SLX25-2FGG484C or XC6SLX100-2FGG484C.
I am a fairly new Electrical Engineer (1.5 years of experience), and I do not have much experience with FPGAs aside from a couple digital courses taken when I was in school. What are some of the particular challenges associated with the change other than altering the code for the new I/Os, and clock speed, and adjusting the pin locations on the PCBs? Are there better FPGA replacements than those listed?
08-30-2017 09:06 AM
All of that is at xilinx.com. Just search for the items you need, it is all there.
08-30-2017 10:12 AM
You have a complicated task for the very first time. Below are some steps for such changes:
Hope this will help,
09-10-2017 07:25 AM
I would start by opening up the existing designs and looking at the resource utilization. There are some differences in the FPGA families that make simple data sheet comparisons difficult when porting a design. For example, the size of look-up tables (4-input vs 6-input) is taken into account when the device's "logic cell" count is calculated. While this gives a better feel of the FPGA's logic complexity, you don't always achieve the multiplier used between logic cell equivalents and actual physical LUTs. A more conservative approach is to find a device that has as least as many LUTs as the original, even if those LUTs are larger and could conceivably handle more code per LUT. Also block RAM size varies. Again, just looking at total Kbits of block RAM misses the point that your design needs some RAMs to be independent of others. Bigger block RAMs may not offer you the opportunity to use all of their bits. So again look for a device that has as many block RAMs or more than the original. I/O is fairly straightforward, however newer parts have some different restrictions (all banks are not necessarily the same). For example Spartan 6 has some banks that don't have as high drive capacity for LVCMOS and others that don't support LVDS outputs.
All that being said, the ideal way to do this is to actually run your design through the tools with the new part selected, so you can see if it fits and meets timing. This probably means at least porting to a more recent version of ISE to get proper support for the new device. If you're already using ISE 10.1.03, this might be not too difficult. If you're on much older tools, there could be some effort to get the design to build properly under the newer tools. This also depends on how you entered the design. Schematic designs are not very portable. HDL designs written in behavioral style are most portable. Designs using IP cores will also require some effort (and possibly expense) to port.
09-10-2017 12:02 PM
09-10-2017 05:27 PM
@lberhold Just a quick note that the others haven't covered: given the option, the Artix 7 is probably a better device to select than the Spartan 6. This is primarily because the Spartan 6 is only supported in ISE (which no longer gets updates), while the Artix 7 is supported in both ISE and the replacement tool, Vivado. This would open up the option of switching to Vivado now, or bringing the design over to the Artix 7 in ISE (probably easier since the current project will be in ISE) and moving to Vivado later.
Apart from that, the Artix 7 is likely to be available for longer than the Spartan 6 (simply because it was released later) and if your product is using Virtex 2 chips then you probably do value long-term availability.