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gowthar
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Registered: ‎11-19-2018

Failed to do clock region partitioning

I ran into the following error while generating the bitstream. There is a question related to this but no solid solution

 

ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net nvdla_top/u_partition_p/u_NV_NVDLA_sdp/u_rdma/u_mrdma/u_eg/u_din/u_sfifo0/nvdla_core_clk_mgate/p_clkgate/Q_uclk_0 in its partition defined by a rectangle from clock region X7Y9 to clock region X7Y9. A clock partition is a rectangular area covering all clock loads and the clock region for its clock root. It may cover the clock source as well. Each clock net needs to use the same routing track across all clock regions of its partition. In this case, other clock nets are already using resources in one or more clock regions of this partition.

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pthakare
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Registered: ‎08-08-2017

Hi @gowthar

This error is because of multiple reasons.

The probable reasons and resolution is listed in answer record

https://www.xilinx.com/support/answers/67384.html

This forum discussion is also helpful in  debugging this issue

https://forums.xilinx.com/t5/Implementation/Place-30-678-Failed-to-do-clock-region-partitioning-Cannot-find/td-p/836123.

@syeds can you please jump in here and put your suggestions.

Pramod Thakare

 

 

 

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gowthar
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Registered: ‎11-19-2018

I solved the issue but I couldn't find a reason why I was getting this error at the first place...
When I tried using Vivado v2018.2 this error didn't pop up...I was using vivado v2016.2 before....

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