UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,254 Views
Registered: ‎07-07-2017

Finding lut propagation delays and jitter of luts' output

I am using kintex ultrascale. I need the delays of all the components max and min it can give. Like example LUT inside CLB will have some propagation delay ,rise time ,fall time. Is there any document which says the delay of Flip flop or carry ahead or MUX is this much in this series or this board

 

Thanks and Regards

0 Kudos
7 Replies
Explorer
Explorer
1,239 Views
Registered: ‎05-08-2018

Re: Finding lut propagation delays and jitter of luts' output

Nope,

 

The speeds files guarantee delays (max).  Those are the only number you have access to that have any value.

 

Jitter is not a result of different delays:  it is a result of substrate noise from switching, cross talk, and power supply ripple, along with any jitter due to clock sources, and signal integrity issues on your pcb.

 

The LUT is the least of your concerns, as the clock trees are the biggest contributor due to their length, and many buffers.  Although designed to be the least jitter possible, they are still converting AM (voltage noise on power and ground) to PM (jitter).

Tags (1)
1,226 Views
Registered: ‎07-07-2017

Re: Finding lut propagation delays and jitter of luts' output

Thanks for the quick response.

 

The speeds files guarantee delays (max).  Those are the only number you have access to that have any value.

 

Can you share the link to speeds files??

 

 

I have not talked about jitter. Jitter can exist around 100ps even from just clocking wizard(seen it in the oscilloscope). What i want is to know the delay of the element like how the complete signal is shifted like for example in the image attached which is common example of glitch the not gate has 2ns delay and and gate has 1ns delay.

 

I just want to know the delays caused by each element for eg i know the delays caused by ibuf will be 2ns ( which i have known after doing post implementation with simple programs) Similarly can i get the delay of the MUX or

Flip Flop inside CLB ?

 

Thanks in advance.

glitch.png
0 Kudos
Explorer
Explorer
1,219 Views
Registered: ‎05-08-2018

Re: Finding lut propagation delays and jitter of luts' output

Speeds files are accessed ,

 

Through the design tools (ISE for older devices, Vivado for 7 series and newer).  I believe the TCL command is get_net_delay.  Look it up.

0 Kudos
1,211 Views
Registered: ‎06-21-2017

Re: Finding lut propagation delays and jitter of luts' output

Your diagram is not realistic.  For instance, you have t=0 at both the source end and the destination end of a signal.  Routing delay is often larger that logic delay in an FPGA.  Also, the inverter would almost certainly be absorbed into the same LUT ad the NAND gate.  As for the glitch, it's bound to happen.  If you are doing synchronous design and have a register on either side of the circuit, the tools will tell you if there is a problem. 

0 Kudos
Historian
Historian
1,210 Views
Registered: ‎01-23-2009

Re: Finding lut propagation delays and jitter of luts' output

Whatever you are trying to do that requires this kind of information, my suggestion to you is "don't".

 

These idealized concepts (of gate delays and fine grained timing) are not realistic - even in the ASIC world, and are far less so in the FPGA world.

 

Delays are never a single number. They are always a range and they vary over process temperature and voltage (PVT). Furthermore signals are not sharp transitions like we like to visualize - they are much more "analog". Therefore, a circuit like the one you show would not likely yield a glitch at all, or it might, or the glitch might not have the amplitude required to completely change the state of the output, or it might on some devices and not others, or at some temperatures and not others, or at some locations on the die or not others...

 

Furthermore, in  the FPGA, there are no primitive NAND gates - everything is done in the LUTs. The LUTs have very complex delays - they are not the same from different inputs, and they are not necessarily the same for rising and falling edges. Also, the LUT is not an "independent" cell - it is part of the CLB, so there may even be some variation depending on which LUT in the CLB it is, and how it is accessed.

 

More importantly, the largest source of delay in an FPGA is not the LUT, it is the routing channels. The routing channel delays are highly variable - not just on PVT, but also on how the tools routed a particular net. This is very hard to control - a different route can change timing by several orders of magnitude more than the delay through a LUT.

 

FPGAs are primarily designed for the implementation of synchronous digital designs. They are excelllent at doing so, and the tools are aimed almost exclusively for building these systems. Any time you try and do something non-synchronous, you will end up fighting the FPGA architecture and fighting the tools even more.

 

Again, my suggestion is "don't"!

 

Avrum

1,176 Views
Registered: ‎07-07-2017

Re: Finding lut propagation delays and jitter of luts' output

@avrumw@bruce_karaffa@alesea

 

Thanks.

 

@avrumwI agree that routing delays cause more delay than logic delay. But vivado automatically takes care of those most of the times for smaller design. i hope i am not wrong about that. I want to know only the delay caused by it. I am ok with the range also.

 

@bruce_karaffaIt places in the same LUT. But this is for simple design. suppose we use MUX , Carry chain they will add some propagation delay. i just want to know that. I remember seeing the document somewhere with the specs now i couldnt find it. Dont know whether it is removed etc.

 

@aleseaI will try get_nets_delay .

 

Thanks all for your responses. Please help me to find out what i am looking for.

0 Kudos
Scholar drjohnsmith
Scholar
1,161 Views
Registered: ‎07-09-2009

Re: Finding lut propagation delays and jitter of luts' output

There is no such thing as component delays , or such like. nor max / min times .

 

There used to be in the good old logic chip days, but not in these custom days.

 

You write in a high level language, such as VHDL,

    and set timing constraints, in the UCF or XDC files.

 

The tools then take this and synthesise the logic to meet these timings and function.

    The tools do this taking into account all the min / max timings over the operating temperatures / voltages / process variations 

          

each run will be different but meet the specifications you give. 

 

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos