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msdarvishi
Explorer
Explorer
3,942 Views
Registered: ‎03-06-2014

Frequency measurement of a high frequency oscillator made in FPGA

Dear all,

I am using Vivado 2016.1 targeting an Artix-7 FPGA. I have implemented a ring oscillator inside the FPGA that oscillates at almost high frequency of 500 MHz. Now, I would like to design a frequency meter and implement it in order to measure that frequency. I know the concepts of frequency measurement and I had a look on this course project:

https://www.google.ca/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwi98o3T8fTTAhUT52MKHWUgDboQFggpMAA&url=https%3A%2F%2Fwww.researchgate.net%2Ffile.PostFileLoader.html%3Fid%3D587b7ac6cbd5c2311f1c2079%26assetKey%3DAS%253A450786841...

The author used a hyprid technique in order to measure the frequency of a high frequency signal. In most parts of the PDF file, he mentioned about the .vhd code sources available in CD but I did not see anything related to them ! Does anyone by chance got the source files of this project or can anyone help me to quickly design and implement a frequency counter for my targhed design, please?

Kind replies and hints are in advance appreciated !

Regards,

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5 Replies
gszakacs
Professor
Professor
3,931 Views
Registered: ‎08-14-2007

Measuring a high frequency like 500 MHz should not require the hybrid method.  How you do it depends on the required accuracy and how much time you have to make the measurement.  For example if you're just looking at long term drift, you could count for 10 seconds and have 0.1 Hz precision (accuracy depends on the stability of your time base).  For a rough measurement you could count for a much shorter period of time like 100 us to get a precision of 2 decimal places in MHz.  In any case the code to do this is quite simple, but the bulk of it runs in the clock domain of the frequency being measured.  In your case that means it needs to be kept simple in order to meet timing.  A typical approach is to have a counter in the reference frequency domain whose high order bit has a period of 1 second (or whatever you want the measurement interval to be).  Then this MSB signal is synchronized to the clock under measurement using two or more flops to reduce the chance of metastable events.  Then delay the synchronized signal to detect rising edges (all in the measured frequency domain) and create a single cycle pulse.  Use that pulse to reset a counter, while loading its prior value into the result register.  The counter and result register need sufficient bits for the maximum frequency.

-- Gabor
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msdarvishi
Explorer
Explorer
3,922 Views
Registered: ‎03-06-2014

Dear @garywangsz

 

Thanks for your reply and explanation. Can you guide me with an example code based on the explanation that you have made? I have no idea about it !

 

Thanks,

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chapman
Xilinx Employee
Xilinx Employee
3,874 Views
Registered: ‎09-05-2007

Attached is a reference design that I prepared for the Spartan-3E Starter Kit eleven years ago which implements a frequency counter. As it happens, it even contained a ring oscillator whose frequency could be measured. I think this reference design provides you with just about all the code and documentation that you should need to create you own design.

 

My only concern is that ~500MHz could be a bit of a challenge especially if you are not familiar with FPGA design. As such, you may like to consider implementing a 'pre-scaler' to initially divide your ~500MHz clock by some factor (e.g. by 10 to ~50MHz) and then measure the lower rate clock (and then re-scale the measurement).

 

 

 

 

Ken Chapman
Principal Engineer, Xilinx UK
msdarvishi
Explorer
Explorer
3,822 Views
Registered: ‎03-06-2014

Dear @chapman,

 

I cordially acknowledge your great help to provide me a way to fin out what I am looking for. I am familiar with high frequency issue in FPGA and this is my field of work. I will go with those files that you kindly shared with me and will give you a feedback on its functionality.

 

Thanks and Regards,

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msdarvishi
Explorer
Explorer
3,819 Views
Registered: ‎03-06-2014

Dear @chapman,

 

The file KCPSM3.zip is no longer available in this link and the design synthesis is failed ! Xilinx might removed the file from server since the FPGA is old...!

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html#design

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