Solved: GTX RX buffer bypass results in shared RXUSRLCK ac...

chris.thomas · ‎08-03-2015

I am switching from using a working GTX transceiver setup using the RX elastic buffer to a new setup that bypasses the elastic buffer (my design does not meet latency requirements with the elastic buffer enabled). I am using the Transceiver Wizard for setup, just like I did earlier to get the design with the elastic buffer working.

The problem I am having is that when I un-check "Enable RX Buffer" in the wizard, the resulting design shares RXUSRCLK among all of the transceivers in the quad, which I do not want, as each lane is independent.

I am doing a "from scratch" design in the wizard, and the only difference between the design with the buffer and the design bypassing the buffer un-checking "Enable RX Buffer".

In the resulting funcsim.v code I see that all RXUSRCLKs are assigned to GT0_RXUSRCLK_OUT:

assign gt0_rxusrclk2_out = gt0_rxusrclk_out;
assign gt0_txusrclk2_out = gt0_txusrclk_out;
assign gt1_rxusrclk2_out = gt0_rxusrclk_out;
assign gt1_rxusrclk_out = gt0_rxusrclk_out;
assign gt1_txusrclk2_out = gt0_txusrclk_out;
assign gt1_txusrclk_out = gt0_txusrclk_out;
assign gt2_rxusrclk2_out = gt0_rxusrclk_out;
assign gt2_rxusrclk_out = gt0_rxusrclk_out;
assign gt2_txusrclk2_out = gt0_txusrclk_out;
assign gt2_txusrclk_out = gt0_txusrclk_out;
assign gt3_rxusrclk2_out = gt0_rxusrclk_out;
assign gt3_rxusrclk_out = gt0_rxusrclk_out;
assign gt3_txusrclk2_out = gt0_txusrclk_out;
assign gt3_txusrclk_out = gt0_txusrclk_out;

Am I misunderstanding how the GTX quad works when the buffer is bypassed? I know that RXOUTCLK is set to RXOUTCLKPMA, which stands to reason that each transceiver should be able to have its own RXUSRCLK.

I have searched these forums but have not been able to find an answer to this, so thank you for any help!

venkata · ‎08-03-2015

In the wizard, if you are enabling multiple GT's it will understand it as a multi-lane use case. So it will generate buffer bypass logic for multi-lane use case.

You will need to generate a single lane design and instantiate it multiple times.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

vuppala · ‎08-03-2015

Hi @chris.thomas

See the section "Using RX Buffer Bypass in Multi-Lane Manual Mode (GTX and GTH Transceivers)" in the following user guide: http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf (page no. 252)

Thanks,

Vinay

--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

chris.thomas · ‎08-03-2015

Hi Vinay,
Thank you for the quick response! I have been referencing this section of UG476, however I can't use the master/slave method because each lane is independent, i.e. they are different speeds and from different sources.

What I'm trying to get to are four lanes, each with their own RXUSRCLK. It seems like this should be possible since each lane has its own RXOUTCLKPMA, but the wizard isn't getting me there.

Any ideas?

Best,
Chris

venkata · ‎08-03-2015

In the wizard, if you are enabling multiple GT's it will understand it as a multi-lane use case. So it will generate buffer bypass logic for multi-lane use case.

You will need to generate a single lane design and instantiate it multiple times.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

chris.thomas · ‎08-03-2015

Ok. I guess it did not really seem like the wizard was doing this when I generated the design using the elastic buffer - it gave me a separate RXUSRCLK for each lane.

I will try generating four separate single-lane designs (in the same quad) as you suggest.

Thanks for your help.

chris.thomas · ‎08-04-2015

Just to make sure that I am clear on the process here, this is what I think I have to do:

1. use the wizard four times to generate four separate cores, one for each lane, all in the same quad

2. ignore the top-level of the generated cores (since they all need to be in the same quad)

3. ignore the *support.v level of the generated cores

4. build my own quad top-level with instantiations for each lane, plus usrclk_source, reset, and common instantiations

5. build a new constraints file, since the .xci and .dcp files will no longer be useful

6. synthesize the IP (I am doing batch synthesis)

7. synthesize the rest of the design

Is this right, or is there a better methodology?

chris.thomas · ‎08-07-2015

For anyone else that may be trying to do something similar, I would not recommend my procedure above.

Instead, generate one quad with four transceivers and one quad with a single transceiver, with both setup to bypass the RX/TX buffers.

Then modify the *_gt_usrclk_source.v file of the 4-lane quad to get independent RX/TX clocks.

Next, in *_init.v file of the 4-lane quad, replace the instantiations (and associated assigns) for the RX and TX manual phase align FSMs (*_manual_phase_align.v) with instantiations (and associated assigns) for the auto phase align FSMs from the *_init.v file of the 1-lane quad (*_auto_phase_align.v). Since the 4-lane design shares some outputs from the phase alignment FSMs with all lanes, you will need to search/replace these signals to make sure all 4 lanes are independent.

Remove the *manual_phase_align.v files from the 4-lane quad example folder and replace with the *auto_phase_align.v file from the 1-lane quad example folder.

Finally, open the *_multi_gt.v file for the 4-lane quad and change the PCS_RSVD_ATTR_IN to clear bits 1 and 2, as per UG476 single-lane buffer bypass instructions.

While the .dcp is no longer useful after these changes, the .xci constraints will still work in your synthesis.

If you want a new funcsim Verilog model, you will need to write it out from Vivado after synthesis.

I can provide more detailed instructions if anyone needs them.

feldmanilia223 · ‎12-20-2018

@chris.thomas wrote:
For anyone else that may be trying to do something similar, I would not recommend my procedure above.

Instead, generate one quad with four transceivers and one quad with a single transceiver, with both setup to bypass the RX/TX buffers.

Then modify the *_gt_usrclk_source.v file of the 4-lane quad to get independent RX/TX clocks.
Next, in *_init.v file of the 4-lane quad, replace the instantiations (and associated assigns) for the RX and TX manual phase align FSMs (*_manual_phase_align.v) with instantiations (and associated assigns) for the auto phase align FSMs from the *_init.v file of the 1-lane quad (*_auto_phase_align.v). Since the 4-lane design shares some outputs from the phase alignment FSMs with all lanes, you will need to search/replace these signals to make sure all 4 lanes are independent.
Remove the *manual_phase_align.v files from the 4-lane quad example folder and replace with the *auto_phase_align.v file from the 1-lane quad example folder.
Finally, open the *_multi_gt.v file for the 4-lane quad and change the PCS_RSVD_ATTR_IN to clear bits 1 and 2, as per UG476 single-lane buffer bypass instructions.

While the .dcp is no longer useful after these changes, the .xci constraints will still work in your synthesis.

If you want a new funcsim Verilog model, you will need to write it out from Vivado after synthesis.

I can provide more detailed instructions if anyone needs them.

Hi I am trying to do the same thing to make quad design TX/RX lanes independent to each other. I have been editing the *_init.v file as per changes recommended.

Since I am using the generated XCI how do I make to pick up my edited *_init.v file instead of the example one?

I am a bit surprised that xilinx haven't implemented an option to make the RX/TX channels independent to each other respectively. When you dig deeper no matter what you try using the IP generator you will still have shared signals.

chris.thomas · ‎12-20-2018

Hi feldmanilia223 ,

In my case I am reading all of the generated and modified Verilog files manually then using the .xdc file for constraints. I am not using the .xci file at all, but it may be possible. I have had good luck using this method for a long time now. Let me know if you have any question on this.

Best,

Chris

feldmanilia223 · ‎12-21-2018

Hi Chris

I guessed so. I am slowly working through it but if I do have any question I will ask for sure.

Thank you for getting back to me.

feldmanilia223 · ‎01-15-2019

@chris.thomas wrote:
Hi feldmanilia223 ,
In my case I am reading all of the generated and modified Verilog files manually then using the .xdc file for constraints. I am not using the .xci file at all, but it may be possible. I have had good luck using this method for a long time now. Let me know if you have any question on this.
Best,
Chris

Hi Chris

I was performing simulation on the 4 independent GTP channels configured as per your instructions. I have noticed at around 1.32ms the clocks from the GTP module gt1_rxoutclk, gt2_rxoutclk and gt3_rxoutclk have stopped running while gt0_rxoutclk is still running I am clueless as to why. All the RXOUTCLK signals for the 4 channels start running at 15us.

Have I forgotten to set something in _gt_gt.v? Is there something I can check to understand what is going on?

Thanks

chris.thomas · ‎01-15-2019

It is a little surprising that all the clocks are running from 15us until 1.32ms - that seems like a long time without knowing what your clock rates are. Are the clock rates a consistent frequency during this whole time, i.e. are the clocks getting faster or slower between the time they start and the time they stop? If so, this might indicate that the reference clock is not toggling. Another thing to look at would be the results of the auto-phase-alignment. The auto-phase-align block for each lane has several signals worth reviewing: RUN_PHALIGNMENT, PHASE_ALIGNMENT_DONE, PHALIGNDONE. It might be worth comparing these signals between the working lane 0 and the other lanes.Below are the detailed notes I took when I went through this. It is likely that some of the signals and filenames have changed with newer versions of the Wizard, since I last did this several years ago. But at least this includes every step I took along the way from customizing the IP in the Wizard through the hand-edits to the resulting IP, hope it helps:

1.1.1.1 Customize the multi-lane IP

Component Name: gtx_quad3

1.1.1.2 GT Selection

GT Type: GTX

Shared Logic: Include shared logic in core

1.1.1.3 Line Rate, RefClk Selection

Protocol: Start from scratch

TX

Line Rate: 1 Gbps

TX off: unchecked

Reference Clock: 100 MHz

RX

Line Rate: 1 Gbps

RX off: unchecked

Reference Clock 100 MHz

Quad column: Right column

Use common DRP: unchecked

Image: Quad 0, GTX_X0Y0 + X0Y1 + X0Y2 + X0Y3, REFCLK1_Q0

PLL Selection

TX: CPLL

RX: CPLL

Transceiver selection

Use GTX X0Y12, X0Y13, X0Y14, X0Y15: checked

TX Clock source: REFCLK1_Q3

RX Clock source: REFCLK1_Q3

Advanced clocking option: unchecked

Vivado lab tools: unchecked

Active Transceivers = 4

1.1.1.4 Encoding and Clocking

TX

External Data Width: 20 bits

Encoding: None

Internal Data Width: 20 bits

RX

External Data Width: 20 bits

Encoding: None

Internal Data Width: 20 bits

Use DRP: checked

DRP/System Clock Frequency: 100 MHz

Optional Ports

None checked

Synchronization and Clocking

TX

Enable TX Buffer: unchecked

TX Buffer Bypass Mode: Auto

TXUSRCLK Source: TXOUTCLK

TXOUTCLK Source: Use TXPLLREFCLK checked

RX

Enable RX Buffer: unchecked

RX Buffer Bypass Mode: Auto

RXUSRCLK Source: RXOUTCLK

RXOUTCLK Source: Use RXPLLREFCLK unchecked

Optional Ports

Checked: RXPMARESET, RXCDRHOLD, TXSYSCLKSEL, RXSYSCLKSEL, CPLLPD, TXRATE, RXRATE

1.1.1.4.1 Comma Alignment and Equalization

RX Comma Alignment

Uncheck all

Termination and Equalization

Differential Swing and Emphasis Mode: Custom

RX Equalization

Mode: LPM-Auto

Automatic Gain Control: Auto

RX Termination

Voltage: Programmable

Trim Value: 800 mV

Optional Ports

Uncheck all

1.1.1.4.2 PCIe, SATA, PRBS

PCIe Express and SATA

Enable PCI Express: unchecked

SATA COM Sequence: n/a

PCI Express Parameters

Transition Time: n/a

Optional Ports

Check TXELECIDLE, TXDETECTRX, PHYSTATUS, RXSTATUS

All other unchecked

OOB signalling and PRBS

Use RX OOB Signal Detection: checked

PRBS: all unchecked

1.1.1.4.3 CB and CC Sequence

Channel Bonding

All unchecked

Clock correction

All unchecked

1.1.1.4.4 Run

Click OK until the synthesis begins. Synthesis will take several minutes to run.

1.1.1.5 Customize the single-lane IP

Component Name: gtx_quad3_lane0

1.1.1.6 GT Selection

GT Type: GTX

Shared Logic: Include shared logic in core

1.1.1.7 Line Rate, RefClk Selection

Protocol: Start from scratch

TX

Line Rate: 1 Gbps

TX off: unchecked

Reference Clock: 100 MHz

RX

Line Rate: 1 Gbps

RX off: unchecked

Reference Clock 100 MHz

Quad column: Right column

Use common DRP: unchecked

Image: Quad 0, GTX_X0Y12 (only)

PLL Selection

TX: CPLL

RX: CPLL

Transceiver selection

Use GTX X0Y12: checked

TX Clock source: REFCLK1_Q3

RX Clock source: REFCLK1_Q3

Advanced clocking option: unchecked

Vivado lab tools: unchecked

Active Transceivers = 1

1.1.1.8 Encoding and Clocking

TX

External Data Width: 20 bits

Encoding: None

Internal Data Width: 20 bits

RX

External Data Width: 20 bits

Encoding: None

Internal Data Width: 20 bits

Use DRP: checked

DRP/System Clock Frequency: 100 MHz

Optional Ports

None checked

Synchronization and Clocking

TX

Enable TX Buffer: unchecked

TX Buffer Bypass Mode: Auto

TXUSRCLK Source: TXOUTCLK

TXOUTCLK Source: Use TXPLLREFCLK checked

RX

Enable RX Buffer: unchecked

RX Buffer Bypass Mode: Auto

RXUSRCLK Source: RXOUTCLK

RXOUTCLK Source: Use RXPLLREFCLK unchecked

Optional Ports

Checked: RXPMARESET, RXCDRHOLD, TXSYSCLKSEL, RXSYSCLKSEL, CPLLPD, TXRATE, RXRATE

1.1.1.8.1 Comma Alignment and Equalization

RX Comma Alignment

Uncheck all

Termination and Equalization

Differential Swing and Emphasis Mode: Custom

RX Equalization

Mode: LPM-Auto

Automatic Gain Control: Auto

RX Termination

Voltage: Programmable

Trim Value: 800 mV

Optional Ports

Uncheck all

1.1.1.8.2 PCIe, SATA, PRBS

PCIe Express and SATA

Enable PCI Express: unchecked

SATA COM Sequence: n/a

PCI Express Parameters

Transition Time: n/a

Optional Ports

Check TXELECIDLE, TXDETECTRX, PHYSTATUS, RXSTATUS

All other unchecked

OOB signalling and PRBS

Use RX OOB Signal Detection: checked

PRBS: all unchecked

1.1.1.8.3 CB and CC Sequence

Channel Bonding

All unchecked

Clock correction

All unchecked

1.1.1.8.4 Run

Click OK until the synthesis begins. Synthesis will take several minutes to run. When it is complete, close Vivado.

1.1.1.8.5 Modify the IP source code

Go to the folder GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3.

Open the gtx_quad3_gt_usrclk_source.v for editing.

Find the BUFG instantiations for gt0_txoutclk and gt0_rxoutclk:

BUFG txoutclk_bufg0_i

(

.I (gt0_txoutclk_i),

.O (gt0_txusrclk_i)

);

BUFG rxoutclk_bufg1_i

(

.I (gt0_rxoutclk_i),

.O (gt0_rxusrclk_i)

);

Add the following instantiations for rx/tx clocks for gt1, gt2, and gt3 immediately after the previous instantiations:

BUFG txoutclk_bufg2_i

(

.I (gt1_txoutclk_i),

.O (gt1_txusrclk_i)

);

BUFG rxoutclk_bufg3_i

(

.I (gt1_rxoutclk_i),

.O (gt1_rxusrclk_i)

);

BUFG txoutclk_bufg4_i

(

.I (gt2_txoutclk_i),

.O (gt2_txusrclk_i)

);

BUFG rxoutclk_bufg5_i

(

.I (gt2_rxoutclk_i),

.O (gt2_rxusrclk_i)

);

BUFG txoutclk_bufg6_i

(

.I (gt3_txoutclk_i),

.O (gt3_txusrclk_i)

);

BUFG rxoutclk_bufg7_i

(

.I (gt3_rxoutclk_i),

.O (gt3_rxusrclk_i)

);

Find the assignments to the outputs that immediately follow:

assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i;

assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i;

assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i;

assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i;

assign GT1_TXUSRCLK_OUT = gt0_txusrclk_i;

assign GT1_TXUSRCLK2_OUT = gt0_txusrclk_i;

assign GT1_RXUSRCLK_OUT = gt0_rxusrclk_i;

assign GT1_RXUSRCLK2_OUT = gt0_rxusrclk_i;

assign GT2_TXUSRCLK_OUT = gt0_txusrclk_i;

assign GT2_TXUSRCLK2_OUT = gt0_txusrclk_i;

assign GT2_RXUSRCLK_OUT = gt0_rxusrclk_i;

assign GT2_RXUSRCLK2_OUT = gt0_rxusrclk_i;

assign GT3_TXUSRCLK_OUT = gt0_txusrclk_i;

assign GT3_TXUSRCLK2_OUT = gt0_txusrclk_i;

assign GT3_RXUSRCLK_OUT = gt0_rxusrclk_i;

assign GT3_RXUSRCLK2_OUT = gt0_rxusrclk_i;

Change them so that they are independent clocks for each lane:

assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i;

assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i;

assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i;

assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i;

assign GT1_TXUSRCLK_OUT = gt1_txusrclk_i;

assign GT1_TXUSRCLK2_OUT = gt1_txusrclk_i;

assign GT1_RXUSRCLK_OUT = gt1_rxusrclk_i;

assign GT1_RXUSRCLK2_OUT = gt1_rxusrclk_i;

assign GT2_TXUSRCLK_OUT = gt2_txusrclk_i;

assign GT2_TXUSRCLK2_OUT = gt2_txusrclk_i;

assign GT2_RXUSRCLK_OUT = gt2_rxusrclk_i;

assign GT2_RXUSRCLK2_OUT = gt2_rxusrclk_i;

assign GT3_TXUSRCLK_OUT = gt3_txusrclk_i;

assign GT3_TXUSRCLK2_OUT = gt3_txusrclk_i;

assign GT3_RXUSRCLK_OUT = gt3_rxusrclk_i;

assign GT3_RXUSRCLK2_OUT = gt3_rxusrclk_i;

Save this file and open the file gtx_quad3_init.v. In another window, go to the GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3_lane0 folder. Open the file gtx_quad3_lane0_init.v. The manual phase alignment blocks used in the multi-lane cores will be replaced with the automatic phase alignment blocks used in the single-lane core.

In the multi-lane file gtx_quad3_init.v, find the following code and delete it:

//Manual

gtx_quad3_TX_MANUAL_PHASE_ALIGN #

(

.NUMBER_OF_LANES (4),

.MASTER_LANE_ID (0)

)

gt0_tx_manual_phase_i

(

.STABLE_CLOCK (sysclk_in),

.RESET_PHALIGNMENT (U0_rst_tx_phalignment_i),

.RUN_PHALIGNMENT (U0_run_tx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt0_tx_phalignment_done_i),

.TXDLYSRESET (U0_TXDLYSRESET),

.TXDLYSRESETDONE (U0_TXDLYSRESETDONE),

.TXPHINIT (U0_TXPHINIT),

.TXPHINITDONE (U0_TXPHINITDONE),

.TXPHALIGN (U0_TXPHALIGN),

.TXPHALIGNDONE (U0_TXPHALIGNDONE),

.TXDLYEN (U0_TXDLYEN)

);

assign gt0_txphdlyreset_i = tied_to_ground_i;

assign gt0_txphalignen_i = tied_to_vcc_i;

assign gt0_txdlysreset_i = U0_TXDLYSRESET[0];

assign gt0_txphinit_i = U0_TXPHINIT[0];

assign gt0_txphalign_i = U0_TXPHALIGN[0];

assign gt0_txdlyen_i = U0_TXDLYEN[0];

assign U0_TXDLYSRESETDONE[0] = gt0_txdlysresetdone_i;

assign U0_TXPHINITDONE[0] = gt0_txphinitdone_i;

assign U0_TXPHALIGNDONE[0] = gt0_txphaligndone_i;

assign gt1_txdlysreset_i = U0_TXDLYSRESET[1];

assign gt1_txphinit_i = U0_TXPHINIT[1];

assign gt1_txphalign_i = U0_TXPHALIGN[1];

assign gt1_txphalignen_i = tied_to_vcc_i;

assign gt1_txphdlyreset_i = tied_to_ground_i;

assign gt1_txdlyen_i = tied_to_ground_i;

assign U0_TXDLYSRESETDONE[1] = gt1_txdlysresetdone_i;

assign U0_TXPHINITDONE[1] = gt1_txphinitdone_i;

assign U0_TXPHALIGNDONE[1] = gt1_txphaligndone_i;

assign gt2_txdlysreset_i = U0_TXDLYSRESET[2];

assign gt2_txphinit_i = U0_TXPHINIT[2];

assign gt2_txphalign_i = U0_TXPHALIGN[2];

assign gt2_txphalignen_i = tied_to_vcc_i;

assign gt2_txphdlyreset_i = tied_to_ground_i;

assign gt2_txdlyen_i = tied_to_ground_i;

assign U0_TXDLYSRESETDONE[2] = gt2_txdlysresetdone_i;

assign U0_TXPHINITDONE[2] = gt2_txphinitdone_i;

assign U0_TXPHALIGNDONE[2] = gt2_txphaligndone_i;

assign gt3_txdlysreset_i = U0_TXDLYSRESET[3];

assign gt3_txphinit_i = U0_TXPHINIT[3];

assign gt3_txphalign_i = U0_TXPHALIGN[3];

assign gt3_txphalignen_i = tied_to_vcc_i;

assign gt3_txphdlyreset_i = tied_to_ground_i;

assign gt3_txdlyen_i = tied_to_ground_i;

assign U0_TXDLYSRESETDONE[3] = gt3_txdlysresetdone_i;

assign U0_TXPHINITDONE[3] = gt3_txphinitdone_i;

assign U0_TXPHALIGNDONE[3] = gt3_txphaligndone_i;

assign U0_run_tx_phalignment_i = gt0_run_tx_phalignment_i

&& gt1_run_tx_phalignment_i

&& gt2_run_tx_phalignment_i

&& gt3_run_tx_phalignment_i

;

assign U0_rst_tx_phalignment_i = gt0_rst_tx_phalignment_i

|| gt1_rst_tx_phalignment_i

|| gt2_rst_tx_phalignment_i

|| gt3_rst_tx_phalignment_i

;

In the single-lane file gtx_quad3_lane0_init.v, copy the following code:

//Auto

assign gt0_txphdlyreset_i = tied_to_ground_i;

assign gt0_txphalignen_i = tied_to_ground_i;

assign gt0_txdlyen_i = tied_to_ground_i;

assign gt0_txphalign_i = tied_to_ground_i;

assign gt0_txphinit_i = tied_to_ground_i;

gtx_quad3_lane0_AUTO_PHASE_ALIGN

gt0_tx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt0_run_tx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt0_tx_phalignment_done_i),

.PHALIGNDONE (gt0_txphaligndone_i),

.DLYSRESET (gt0_txdlysreset_i),

.DLYSRESETDONE (gt0_txdlysresetdone_i),

.RECCLKSTABLE (tied_to_vcc_i)

);

Paste four copies of this code into the file gtx_quad3_init.v where the old code was deleted. Update index of all signals as well as the instance names:

//Auto

assign gt0_txphdlyreset_i = tied_to_ground_i;

assign gt0_txphalignen_i = tied_to_ground_i;

assign gt0_txdlyen_i = tied_to_ground_i;

assign gt0_txphalign_i = tied_to_ground_i;

assign gt0_txphinit_i = tied_to_ground_i;

assign gt1_txphdlyreset_i = tied_to_ground_i;

assign gt1_txphalignen_i = tied_to_ground_i;

assign gt1_txdlyen_i = tied_to_ground_i;

assign gt1_txphalign_i = tied_to_ground_i;

assign gt1_txphinit_i = tied_to_ground_i;

assign gt2_txphdlyreset_i = tied_to_ground_i;

assign gt2_txphalignen_i = tied_to_ground_i;

assign gt2_txdlyen_i = tied_to_ground_i;

assign gt2_txphalign_i = tied_to_ground_i;

assign gt2_txphinit_i = tied_to_ground_i;

assign gt3_txphdlyreset_i = tied_to_ground_i;

assign gt3_txphalignen_i = tied_to_ground_i;

assign gt3_txdlyen_i = tied_to_ground_i;

assign gt3_txphalign_i = tied_to_ground_i;

assign gt3_txphinit_i = tied_to_ground_i;

gtx_quad3_AUTO_PHASE_ALIGN

gt0_tx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt0_run_tx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt0_tx_phalignment_done_i),

.PHALIGNDONE (gt0_txphaligndone_i),

.DLYSRESET (gt0_txdlysreset_i),

.DLYSRESETDONE (gt0_txdlysresetdone_i),

.RECCLKSTABLE (tied_to_vcc_i)

);

gtx_quad3_AUTO_PHASE_ALIGN

gt1_tx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt1_run_tx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt1_tx_phalignment_done_i),

.PHALIGNDONE (gt1_txphaligndone_i),

.DLYSRESET (gt1_txdlysreset_i),

.DLYSRESETDONE (gt1_txdlysresetdone_i),

.RECCLKSTABLE (tied_to_vcc_i)

);

gtx_quad3_AUTO_PHASE_ALIGN

gt2_tx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt2_run_tx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt2_tx_phalignment_done_i),

.PHALIGNDONE (gt2_txphaligndone_i),

.DLYSRESET (gt2_txdlysreset_i),

.DLYSRESETDONE (gt2_txdlysresetdone_i),

.RECCLKSTABLE (tied_to_vcc_i)

);

gtx_quad3_AUTO_PHASE_ALIGN

gt3_tx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt3_run_tx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt3_tx_phalignment_done_i),

.PHALIGNDONE (gt3_txphaligndone_i),

.DLYSRESET (gt3_txdlysreset_i),

.DLYSRESETDONE (gt3_txdlysresetdone_i),

.RECCLKSTABLE (tied_to_vcc_i)

);

Also, search for all occurances of the signal gt0_tx_phalignment_done_i in gtx_quad3_init.v, as it is shared with the startup state machines in the multi-lane case. This signal must be made unique to each state machine:

gt1_txresetfsm_i

(

…

.PHALIGNMENT_DONE (gt1_tx_phalignment_done_i),

gt2_txresetfsm_i

(

…

.PHALIGNMENT_DONE (gt2_tx_phalignment_done_i),

gt3_txresetfsm_i

(

…

.PHALIGNMENT_DONE (gt3_tx_phalignment_done_i),

Now do the same thing for the RX side that was just done for the TX side. In the multi-lane file gtx_quad3_init.v, find the following code and delete it:

//Manual

gtx_quad3_RX_MANUAL_PHASE_ALIGN #

(

.NUMBER_OF_LANES (4),

.MASTER_LANE_ID (0)

)

gt0_rx_manual_phase_i

(

.STABLE_CLOCK (sysclk_in),

.RESET_PHALIGNMENT (U0_rst_rx_phalignment_i),

.RUN_PHALIGNMENT (U0_run_rx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt0_rx_phalignment_done_i),

.RXDLYSRESET (U0_RXDLYSRESET),

.RXDLYSRESETDONE (U0_RXDLYSRESETDONE),

.RXPHALIGN (U0_RXPHALIGN),

.RXPHALIGNDONE (U0_RXPHALIGNDONE),

.RXDLYEN (U0_RXDLYEN)

);

assign gt0_rxphdlyreset_i = tied_to_ground_i;

assign gt0_rxphalignen_i = tied_to_vcc_i;

assign gt0_rxdlysreset_i = U0_RXDLYSRESET[0];

assign gt0_rxphalign_i = U0_RXPHALIGN[0];

assign gt0_rxdlyen_i = U0_RXDLYEN[0];

assign U0_RXDLYSRESETDONE[0] = gt0_rxdlysresetdone_i;

assign U0_RXPHALIGNDONE[0] = gt0_rxphaligndone_i;

assign gt1_rxdlysreset_i = U0_RXDLYSRESET[1];

assign gt1_rxphalign_i = U0_RXPHALIGN[1];

assign gt1_rxphalignen_i = tied_to_vcc_i;

assign gt1_rxphdlyreset_i = tied_to_ground_i;

assign gt1_rxdlyen_i = tied_to_ground_i;

assign U0_RXDLYSRESETDONE[1] = gt1_rxdlysresetdone_i;

assign U0_RXPHALIGNDONE[1] = gt1_rxphaligndone_i;

assign gt2_rxdlysreset_i = U0_RXDLYSRESET[2];

assign gt2_rxphalign_i = U0_RXPHALIGN[2];

assign gt2_rxphalignen_i = tied_to_vcc_i;

assign gt2_rxphdlyreset_i = tied_to_ground_i;

assign gt2_rxdlyen_i = tied_to_ground_i;

assign U0_RXDLYSRESETDONE[2] = gt2_rxdlysresetdone_i;

assign U0_RXPHALIGNDONE[2] = gt2_rxphaligndone_i;

assign gt3_rxdlysreset_i = U0_RXDLYSRESET[3];

assign gt3_rxphalign_i = U0_RXPHALIGN[3];

assign gt3_rxphalignen_i = tied_to_vcc_i;

assign gt3_rxphdlyreset_i = tied_to_ground_i;

assign gt3_rxdlyen_i = tied_to_ground_i;

assign U0_RXDLYSRESETDONE[3] = gt3_rxdlysresetdone_i;

assign U0_RXPHALIGNDONE[3] = gt3_rxphaligndone_i;

assign U0_run_rx_phalignment_i = gt0_run_rx_phalignment_i

&& gt1_run_rx_phalignment_i

&& gt2_run_rx_phalignment_i

&& gt3_run_rx_phalignment_i

;

assign U0_rst_rx_phalignment_i = gt0_rst_rx_phalignment_i

|| gt1_rst_rx_phalignment_i

|| gt2_rst_rx_phalignment_i

|| gt3_rst_rx_phalignment_i

;

In the single-lane file gtx_quad3_lane0_init.v, copy the following code:

//Auto

assign gt0_rxphdlyreset_i = tied_to_ground_i;

assign gt0_rxphalignen_i = tied_to_ground_i;

assign gt0_rxdlyen_i = tied_to_ground_i;

assign gt0_rxphalign_i = tied_to_ground_i;

gtx_quad3_lane0_AUTO_PHASE_ALIGN

gt0_rx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt0_run_rx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt0_rx_phalignment_done_i),

.PHALIGNDONE (gt0_rxphaligndone_i),

.DLYSRESET (gt0_rxdlysreset_i),

.DLYSRESETDONE (gt0_rxdlysresetdone_i),

.RECCLKSTABLE (gt0_recclk_stable_i)

);

Paste four copies of this code into the file gtx_quad3_init.v where the old code was deleted. Update index of all signals as well as the instance names:

//Auto

assign gt0_rxphdlyreset_i = tied_to_ground_i;

assign gt0_rxphalignen_i = tied_to_ground_i;

assign gt0_rxdlyen_i = tied_to_ground_i;

assign gt0_rxphalign_i = tied_to_ground_i;

assign gt1_rxphdlyreset_i = tied_to_ground_i;

assign gt1_rxphalignen_i = tied_to_ground_i;

assign gt1_rxdlyen_i = tied_to_ground_i;

assign gt1_rxphalign_i = tied_to_ground_i;

assign gt2_rxphdlyreset_i = tied_to_ground_i;

assign gt2_rxphalignen_i = tied_to_ground_i;

assign gt2_rxdlyen_i = tied_to_ground_i;

assign gt2_rxphalign_i = tied_to_ground_i;

assign gt3_rxphdlyreset_i = tied_to_ground_i;

assign gt3_rxphalignen_i = tied_to_ground_i;

assign gt3_rxdlyen_i = tied_to_ground_i;

assign gt3_rxphalign_i = tied_to_ground_i;

gtx_quad3_AUTO_PHASE_ALIGN

gt0_rx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt0_run_rx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt0_rx_phalignment_done_i),

.PHALIGNDONE (gt0_rxphaligndone_i),

.DLYSRESET (gt0_rxdlysreset_i),

.DLYSRESETDONE (gt0_rxdlysresetdone_i),

.RECCLKSTABLE (gt0_recclk_stable_i)

);

gtx_quad3_AUTO_PHASE_ALIGN

gt1_rx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt1_run_rx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt1_rx_phalignment_done_i),

.PHALIGNDONE (gt1_rxphaligndone_i),

.DLYSRESET (gt1_rxdlysreset_i),

.DLYSRESETDONE (gt1_rxdlysresetdone_i),

.RECCLKSTABLE (gt1_recclk_stable_i)

);

gtx_quad3_AUTO_PHASE_ALIGN

gt2_rx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt2_run_rx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt2_rx_phalignment_done_i),

.PHALIGNDONE (gt2_rxphaligndone_i),

.DLYSRESET (gt2_rxdlysreset_i),

.DLYSRESETDONE (gt2_rxdlysresetdone_i),

.RECCLKSTABLE (gt2_recclk_stable_i)

);

gtx_quad3_AUTO_PHASE_ALIGN

gt3_rx_auto_phase_align_i

(

.STABLE_CLOCK (sysclk_in),

.RUN_PHALIGNMENT (gt3_run_rx_phalignment_i),

.PHASE_ALIGNMENT_DONE (gt3_rx_phalignment_done_i),

.PHALIGNDONE (gt3_rxphaligndone_i),

.DLYSRESET (gt3_rxdlysreset_i),

.DLYSRESETDONE (gt3_rxdlysresetdone_i),

.RECCLKSTABLE (gt3_recclk_stable_i)

);

Also, search for all occurances of the signal gt0_rx_phalignment_done_i in gtx_quad3_init.v, as it is shared with the startup state machines in the multi-lane case. This signal must be made unique to each state machine:

gt1_rxresetfsm_i

(

…

.PHALIGNMENT_DONE (gt1_rx_phalignment_done_i),

gt2_rxresetfsm_i

(

…

.PHALIGNMENT_DONE (gt2_rx_phalignment_done_i),

gt3_rxresetfsm_i

(

…

.PHALIGNMENT_DONE (gt3_rx_phalignment_done_i),

Finally, find and delete the following signal declarations in gtx_quad3_init.v:

// --------------------------- TX Buffer Bypass Signals --------------------

wire mstr0_txsyncallin_i;

wire [3 : 0] U0_TXDLYEN;

wire [3 : 0] U0_TXDLYSRESET;

wire [3 : 0] U0_TXDLYSRESETDONE;

wire [3 : 0] U0_TXPHINIT;

wire [3 : 0] U0_TXPHINITDONE;

wire [3 : 0] U0_TXPHALIGN;

wire [3 : 0] U0_TXPHALIGNDONE ;

wire U0_run_tx_phalignment_i;

wire U0_rst_tx_phalignment_i;

// --------------------------- RX Buffer Bypass Signals --------------------

wire rxmstr0_rxsyncallin_i;

wire [3 : 0] U0_RXDLYEN;

wire [3 : 0] U0_RXDLYSRESET;

wire [3 : 0] U0_RXDLYSRESETDONE;

wire [3 : 0] U0_RXPHALIGN;

wire [3 : 0] U0_RXPHALIGNDONE ;

wire U0_run_rx_phalignment_i;

wire U0_rst_rx_phalignment_i;

Now, delete the multi-lane files:

GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3/gtx_quad3/example_design/gtx_quad3_rx_manual_phase_align.v

GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3/gtx_quad3/example_design/gtx_quad3_tx_manual_phase_align.v

Copy the file:

GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3_lane0/gtx_quad3_lane0/example_design/gtx_quad3_lane0_auto_phase_align.v

To:

GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3/gtx_quad3/example_design/gtx_quad3_auto_phase_align.v

Go to the folder:

GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3/gtx_quad3/example_design

And open the file gtx_quad3_auto_phase_align.v

Find and replace the string “gtx_quad3_lane0” with “gtx_quad3” (5 occurrences)

Save and close.

Go back to the folder:

GTX_Wizard_run/GTX_Wizard_Project/GTX_Wizard_Project.srcs/sources_1/ip/gtx_quad3

Open the file gtx_quad3_multi_gt.v

Search for the string “PCS_RSVD_ATTR_IN” and replace the lines (4 occurrences):

.PCS_RSVD_ATTR_IN (48'h000000000106),

with:

.PCS_RSVD_ATTR_IN (48'h000000000100),

Save and close.

GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes

Re: GTX RX buffer bypass results in shared RXUSRLCK across all lanes