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Adventurer
Adventurer
6,806 Views
Registered: ‎06-25-2015

GTX common usage for two transceivers

Hello, I am using two transceivers located in different quads (117 & 118). I want to use the reference clock attached to the common in quad 118 as my reference clock in quad 117. Do I need to instantiate another common form quad 117 even though the clock is south bound from quad 118? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

HI ,

Yes you need to instantiate a separate common for the  of quad 117. one GTX common can only work with Transceivers  channel in the same quad.

you can use the same ref clk you use for GTX common in the upper quad  by connecting them to southrefclk of the lower Quad.

Thanks
Bharath
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GTX_quad.JPG
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Adventurer
Adventurer
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Registered: ‎06-25-2015

Ok. Thank you for this. I connected the reference clock from quad 118 to gtrefclk1 in quad 117. The router seems to have auto-routed to the correct south bound input. This seemed to have worked. Now I am trying to use both the cpll and qpll to clock the GTX.  I want to use the qpll for rx and cpll for tx. The qpll and cpll have different clock sources. It appears that the received is being clocked correctly from the qpll but the transmitter is not. I do not observe a clock pulse on txoutclk. I have connected the reference clock to gtrefclk1 of the GTX wrapper. What else might I need to consider to make this work properly? Also I am not dynamically changing between qpll and cpll.

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Xilinx Employee
Xilinx Employee
6,669 Views
Registered: ‎05-07-2015

HI @acgropp1

 

ensure that the CPLLREFCLKSEL[2:0] which chooses the ref clock input of the CPLL is driven correctly.
the TXSYSCLKSEL[1:0] should be '00' for CPLL usage.

refer page 37 and 38 of UG476 for GTX channel port descriptions.

Thanks
Bharath
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Adventurer
Adventurer
6,658 Views
Registered: ‎06-25-2015

Okay. Thank you for this. I will look my ensure these are being driven correctly. 

 

Also, if I have a GTX with a cpll (tx) and qpll (rx) where both are driven by the same reference clock, would this behave the same way as a GTX with two qplls or cpll driven with a reference clock.

 

Thank you

 

Adam Gropp

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Xilinx Employee
Xilinx Employee
6,639 Views
Registered: ‎05-07-2015

HI @acgropp1

 

>>would this behave the same way as a GTX with two qplls or cpll driven with a reference clock.

By two qplls, do you mean both rx and tx using the  qpll ref clock? (as one quad will have only one qpll)

depending on application there will certain limitations on one (cpll-tx and qpll-rx) usage w.r.t other(both qpll or both cpll)
For example : the PCIe Gen1 and Gen2 solution was only tested and validated using the CPLL.  hence using QPLL is not recommend.
In HDMI ,application, When using the two Quad PLL (QPLL) types for the HDMI transmitter and receiver, line rate restrictions are introduced due to the VCO range and limited set of multipliers of the QPLL.

Thanks
Bharath
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Adventurer
Adventurer
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Registered: ‎06-25-2015

Hello @nagabhar,

 

Thank you for this. This is good to know. Do all GTX reference clocks have to be supplied from an external source or can the reference clocks be provided using the clocking wizard? My reason for asking this is the GTX in quad 117 can take an external clock from the SMA connectors or from the SGMII. I have not found much information on how to generate 148.5 MHZ clock with the SGMII (I do know that it is used to clock the ethernet core). Thank you for your time.

 

Adam Gropp

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Xilinx Employee
Xilinx Employee
6,625 Views
Registered: ‎05-07-2015

HI @acgropp1

 

Yes, internal clocks can be used as a ref clock for the QPLL/CPLL.  GTGREFCLK  input of GTXE_common and GTXE_channel are used for this.

These reference clock ports have a lower performance compared  to external ref clock input via dedicated MGTREFCLK ping because FPGA  clocking resources can introduce jitter for operation at high data rates.

please refer UG476 in detail,
http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

Thanks
Bharath
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GTGREFCLK.JPG
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Moderator
Moderator
6,587 Views
Registered: ‎02-16-2010

Since this usage is not recommended, VIVADO reports error about this use case.

check this AR
http://www.xilinx.com/support/answers/61656.html
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Xilinx Employee
Xilinx Employee
6,500 Views
Registered: ‎02-14-2014

Hello @acgropp1,

 

Below threads can be helpful

https://forums.xilinx.com/t5/7-Series-FPGAs/GTX-QPLLREFCLKSEL/m-p/713230#M17951

https://forums.xilinx.com/t5/7-Series-FPGAs/GTX-QPLL-Clock-Source/m-p/715629#M18242

Regards,
Ashish
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