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Participant
Participant
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Registered: ‎11-11-2016

Generating an output clock with generic I/O pin KC705

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Good afternoon,

we are trying to generate a LVCMOS 3.3V 20MHz 50% DC output clock from a 100MHz clock derived from a MMCM instantiated within a design for the KC705. The result obtained with an oscilloscope attached to a test point connected to the selected pin with the FMC is yet a non-square wave signal. What are the characteristics for a generic (non HP) pin on the device?The current physical constraints are as follows:

set_property PACKAGE_PIN B18 [get_ports {clk_out}]

set_property OFFCHIP_TERM NONE [get_ports {clk_out}]

set_property IOSTANDARD LVCMOS33 [get_ports {clk_out}]

set_property SLEW FAST [get_ports [get_ports {clk_out}]

set_property DRIVE 16 [get_ports [get_ports {clk_out}]

Thanks in advance, best regards.

 

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Participant
Participant
392 Views
Registered: ‎11-11-2016

Re: Generating an output clock with generic I/O pin KC705

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watari,

Thanks for your reply. The issue was solved generating the signal on a GPIO of a ZedBoard. The image registered on oscilloscope was probably due to the length of the trace from the KC705 to the TP after the FMC connector.

Regards.

View solution in original post

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: Generating an output clock with generic I/O pin KC705

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Hi @eugeth20 

 

Does it directly output clock signal from MMCM ?

If yes, I suggest you to use ODDR primitive.

 

However, it's hard to achive precise waveform, duty is 50:50...

 

Best regards,

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Participant
Participant
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Registered: ‎11-11-2016

Re: Generating an output clock with generic I/O pin KC705

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watari,

 

thanks for your quick reply. We tried to generate first the signal with a clock divider with user logic, set it as input to a BUFG before the OUTBUF. Rising time of the signal is about 15ns.

Successively we generated the signal via the MMCM with the ODDR macro, yet no improvements were found.

Screenshot from oscilloscope is in attachment.

sqw.png
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Mentor
Mentor
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Registered: ‎06-16-2013

Re: Generating an output clock with generic I/O pin KC705

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Hi @eugeth20 

 

Here is example code. Not test.

Would you refer it ?

 

---

u1 ODDR(

.C(clk),

.D1(rise_sig),

.D2(fall_sig),

.CE(1),

.SR(0),

.Q(out)

)

 

assign rise_sig = (counter>2) ? 0: 1;

assgin fall_sig = (counter<2) ? 1: 0;

 

always @(clk) begin

  if (counter==4) begin

    counter <= 0;

  else begin

    counter <= count +1

  end

end

 

Best regards

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Highlighted
Participant
Participant
393 Views
Registered: ‎11-11-2016

Re: Generating an output clock with generic I/O pin KC705

Jump to solution

watari,

Thanks for your reply. The issue was solved generating the signal on a GPIO of a ZedBoard. The image registered on oscilloscope was probably due to the length of the trace from the KC705 to the TP after the FMC connector.

Regards.

View solution in original post

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