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Anonymous
Not applicable
5,436 Views

Generating binary random sequence from 7 series GTx transceivers using KC705 board

Hello,

 

I wish to generate binary random sequence from 7 series GTx transceivers using KC705 board which has Kintex 7 FPGA withourt using any ipcore of wizard. Can someone please give reference resources or reerence design? How shall I proceed?

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eilert
Teacher
Teacher
5,428 Views
Registered: ‎08-14-2007

Hi,

this will become hard without using the Coregen configuration core.

 

So you need to study the 7 series GTx transceivers user guide in detail, and some other helpful papers as well.

After you understood how to deal with the clocking and other settings you can simply attach a wide LFSR to one of the data inputs and that's it.

 

Have a nice synthesis

  Eilert

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Anonymous
Not applicable
5,393 Views

Hi,

 

I customised the 7 series tranceiver ipcore as attached in the xco file. I wsh to generate a 1.25 gbps random sequence from 4 FMC and 1 SMA transceiver on KC705 board. I used the 125 MHz user clock which is on G7 G8 FPGA U1 pins. I have turned the Rx off as I do not wish to use it as a receiver.

 

Please help me out here.

 

Thanks and Regards,

 

Nandish.

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Anonymous
Not applicable
5,386 Views

Hi,

 

The CORE Generator mentions that the core is a pre poduction core. Does that mean I can not download it on FPGA? Please clarify the meaning of pre production core and production core.

 

I am using ISE 13.4. I have attached the screenshot of it.

 

CoreGeneratorScreenshot.jpg

 

Thanks and Regards,

 

Nandish.

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syedz
Moderator
Moderator
5,359 Views
Registered: ‎01-16-2013

Hi,

 

The Status column refers to the life cycle state of the IP core. The status can be any one of the following.

  • Beta: This is IP released into a Beta program. This state allows tools to differentiate between Beta IP and other production level IP.
  • Pre-Production: This state is used for early acceptance of cores used for silicon early acceptance programs.
  • Production: In this state the IP is fully supported and fully tested.
  • Discontinued: Discontinued IP state represents IP core which has been marked as “End-of-Life”. IP in this state are removed from ISE® Design Suite at the major release that occurs one year after the release in which the IP was put in a discontinued state. Refer to the IP data sheet for the recommended alternatives.
  • Superseded: IP in Superseded IP Version have a new version of the IP available. IP versions in this state are removed from ISE Design Suite at the next major release. IP cores in this state are not supported.

Regards,

Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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