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459 Views
Registered: ‎08-03-2018

## Help: Edge alignment or Phase alignment implementation

Hi

I'm using Spartan 6 device with LX9 part number. I have two signals :

The first one has 195.3125 MHZ frequency with 50% duty cycle.

The secend one is unknown. we don't know it's frequency and duty cycle.

Here is the issue : How can i understand that both rising edges are align?

Imagin that i'm shifting the first one and i want to understand whether the rising edges are align or not.

Thank you.

5 Replies
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Teacher
448 Views
Registered: ‎07-09-2009
Are you after a phase / frequency detector ?

How far out is the second signal,
are you using the output of this block to control the unknown signal to align them

if so you need a phased locked loop phase detector.

http://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf

https://slideplayer.com/slide/5961252/

if not,
give us some more details as to what you want to do

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437 Views
Registered: ‎08-03-2018

Hi dear

Ok , i try to explane it ...

I have a signal with 195.3125 MHZ frequency and 50% duty cycle. I made it in my spartan 6 divice (inside it). I am able to shift this signal forward every 25ps (1 step = 25ps , 2 step=50ps , 3 step=75 ps ....).

I want to align the rising edge of this signal with another one which comes from outside and i don't know it's frequency and duty cycle. By shifting the first signal , i want to synchronize the rising edge of first signal with the secend signal.

So, imagin that i shift the first signal , 3 step (3*25=75ps), How can i understand that both rising edges are synchronize (or align) ? How can i detect this ?

Highlighted
Teacher
433 Views
Registered: ‎07-09-2009
you need a phase frequency detector

25 ps is very small , how did you manage to do that inside a relatively slow fpga,
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426 Views
Registered: ‎08-03-2018

Hi

I made it with DCM . See UG382 , chapter 2 .

What is difference between "phase frequency detector" and "phase detector" ?

I know that we use "phase detector" when both signals have a same frequency.

Highlighted
Teacher
409 Views
Registered: ‎07-09-2009
two signals can be frequency locked, ie the same frequency , without being phased locked, i.e the phase between the signals is not defined.

Once you are frequency locked, then, you can be phase locked.
i.e. a known phase difference between the two signals,

it does not necessarily have to be zero degrees. 90 is quiet common,

If you just Xor two signals of the same frequency , then the magnitude of the xor output is proportional to the difference in phase.

have u looked at the references I posted.
this might help further

this one goes back a while
http://application-notes.digchip.com/077/77-43288.pdf

and this is a fuller design of a pll

https://www.xilinx.com/support/documentation/application_notes/xapp854.pdf