From your reset name (poreset = power-ON reset?), it appears you are sending a power-ON reset to the various components of your design. Often, power-ON resets are asynchronous and they cross clock-domains - both of which can cause timing analysis problems.
Usually, a circuit called a reset-bridge is used to bring the power-ON reset into each clock-domain. That is, a separate reset-bridge is needed for each clock domain. The reset-bridge causes the reset in each clock-domain to go ON simultaneously with the power-ON reset and to come OFF synchronously with the clock in the clock-domain. The reset-bridge also acts as a synchronizer and should prevent the timing analysis problems you are seeing. You’ll find details of the reset-bridge and other discussion of resets in <this> post.