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Newbie aderbed
Registered: ‎10-30-2018

Hold violation V5Q in DSP block

I am getting hold time violations within the DSP block in the V5Q FPGA using ISE13.2

It is not clear why the tool is not able to fix it. Can anyone help



Delay (fastest path): -0.188ns (data path)
Source: swot_proc_e/common_e/use_azmpr_g.azimuth_compression_e/BEAMPROC.6.DOTPM/prod_1_0[34:0] (DSP)
Destination: swot_proc_e/common_e/use_azmpr_g.azimuth_compression_e/BEAMPROC.6.DOTPM/prod_1Add_0[28:0] (DSP)
Data Path Delay: -0.188ns (Levels of Logic = 0)
Destination Clock: PROC_CLK rising at 0.000ns

Minimum Data Path: swot_proc_e/common_e/use_azmpr_g.azimuth_compression_e/BEAMPROC.6.DOTPM/prod_1_0[34:0] to swot_proc_e/common_e/use_azmpr_g.azimuth_compression_e/BEAMPROC.6.DOTPM/prod_1Add_0[28:0]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
DSP48_X1Y34.BCIN0 net (fanout=1) 0.000 swot_proc_e/common_e/use_azmpr_g.azimuth_compression_e/BEAMPROC.6.DOTPM/binz_2_1_0(0)
DSP48_X1Y34.CLK Tdspckd_BCINM(-Th) 0.188 swot_proc_e/common_e/use_azmpr_g.azimuth_compression_e/BEAMPROC.6.DOTPM/prod_1Add_0[28:0]
------------------------------------------------- ---------------------------
Total -0.188ns (-0.188ns logic, 0.000ns route)
(100.0% logic, -0.0% route)


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2 Replies
Registered: ‎01-23-2009

Re: Hold violation V5Q in DSP block

Cool - negative data delays!!!


Are the source and the destination on the same clock?


It's been a while since I looked at ISE timing reports - is there a more complete path report (that shows the clock relationships)?


But negative data delays are an odd thing - they shouldn't exist. And this isn't just a little negative (i.e. something you could attribute to rounding errors) - -0.188ns is a pretty large negative delay.


As for why the tool can't fix it - it can't. From the name this looks like a dedicated DSP to DSP carry path (through the BCIN port of the DSP). This is not a general fabric route - this is a dedicated set of connections the BCOUT connections of one DSP cell to the BCIN of the one right above it. The tools have no ability to do anything with this path - the timing is what it is. So the big question is "why does it think the delay is negative????"



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Newbie aderbed
Registered: ‎10-30-2018

Re: Hold violation V5Q in DSP block

thanks for your reply.

You are right, this is an internal path from one DSP to another.

Both source and destination have the same clock source.

I have attached the schematic that shows the path and the clocks.

It is still not clear as to why I am getting this hold violation. Could it be something in the setting that is making it behave like this?

I can't imagine I am the only one who has seen this issue.



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