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sheladiya_vijay
Explorer
Explorer
9,217 Views
Registered: ‎12-10-2012

How can I utilize Memory LUTs as a Logic LUT?

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Hi,

 

I am using Kintex-7 XC7K160T-2FFG676C device with Vivado 2013.4. Since I'm not able to implement my design due over resource utilization, I have attached resourse utilization report generated after synthesis.

 

As per synthesis utilization report, I can see only 14% utilization of LUT as Memory and logic LUT utilization exceeds 100%. So is there a way that Memory LUTs can be utilized as logic LUTs?

 

Thanks,

Vijay

synth_utilization.PNG
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avrumw
Expert
Expert
13,934 Views
Registered: ‎01-23-2009

To answer the original question...

 

All LUTs are able to be used as logic. Rougly 1/4 of them can also be used as memory. Looking at your numbers it says there are 101,400 slice LUTs in the FPGA. Of this, only 35,000 can be used as memory, but all can be used as logic. Your design is trying to use 107,195 as logic and 4,727 as memory - thus a total of 111,922 of the 101,400 are used.

 

This is WAY too much for the device. Vivado is much better than ISE at getting high LUT utilizations, but even at that you should not be targetting more than 85% utilization - you can get a bit more, but it starts getting very difficult to meet timing at higher utilizations.

 

You either have to choose a larger device of simplify your design so that it doesn't use as many LUTs. You may be able to do some recoding that will allow some LUT based logic to be moved to block RAMs (some state machines can) and/or DSP slices (although you are using a good number of DSPs already), but I doubt that this is going to be enough to get this to fit in your device.

 

Avrum

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trenz-al
Scholar
Scholar
9,173 Views
Registered: ‎11-09-2013

just go ahead. the tools will do it all for you at later steps. it does not matter if that you see >100% in synthesis

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sheladiya_vijay
Explorer
Explorer
9,169 Views
Registered: ‎12-10-2012

Hi trenz-al,

 

Thanks for reply...

 

I tried to go for  "Implemention" but it fails and gives error message like,

 

"[Place 30-380] Design has 87327 flops (which belong to 2135 control sets and 0 of them are latches) and 118969 luts. Their placement requires at least 28149 slices but the device has only 25350 slices." 

 

Thanks,

Vijay

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gszakacs
Instructor
Instructor
9,139 Views
Registered: ‎08-14-2007

"2135 control sets"

 

That's a lot of control sets.  This means you have 2,135 different combinations of clock and reset inputs for these flops.  It suggests that your design methodology is not very synchronous and therefore not friendly to FPGA implementation.

-- Gabor
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avrumw
Expert
Expert
13,935 Views
Registered: ‎01-23-2009

To answer the original question...

 

All LUTs are able to be used as logic. Rougly 1/4 of them can also be used as memory. Looking at your numbers it says there are 101,400 slice LUTs in the FPGA. Of this, only 35,000 can be used as memory, but all can be used as logic. Your design is trying to use 107,195 as logic and 4,727 as memory - thus a total of 111,922 of the 101,400 are used.

 

This is WAY too much for the device. Vivado is much better than ISE at getting high LUT utilizations, but even at that you should not be targetting more than 85% utilization - you can get a bit more, but it starts getting very difficult to meet timing at higher utilizations.

 

You either have to choose a larger device of simplify your design so that it doesn't use as many LUTs. You may be able to do some recoding that will allow some LUT based logic to be moved to block RAMs (some state machines can) and/or DSP slices (although you are using a good number of DSPs already), but I doubt that this is going to be enough to get this to fit in your device.

 

Avrum

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sheladiya_vijay
Explorer
Explorer
9,099 Views
Registered: ‎12-10-2012

Hi,

 

Thank you guys... I got my answer. It is really useful information.

 

Thanks,

Vijay

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sivasankar.s
Adventurer
Adventurer
6,632 Views
Registered: ‎06-11-2015

hello all,

 i need to make memory lut as logic lut,,,

 can u tell me me how u have achieved in making it,,

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sunmeng525
Newbie
Newbie
2,729 Views
Registered: ‎03-26-2019

hi guy 

friend,i also meet this question ,my report maybe worse than you ,could you share your method with me 

 

 

 

thanks 

sm

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