10-13-2018 02:05 AM
I am using XC7VX690T and unfortunately bank 33 and 34 were damaged (don't know how). Both inputs and outputs of these two banks are not working. It seems the VCCIO supply was cut off in these two banks (just a guess).
I moved the signals originally assigned to bank 33 and 34 to other working banks. But after generating a new bit file, I found that the whole chip was not working! (I instantiated a CPU in FPGA, but now it can not be accessed by JTAG).
My question is, may it be the bank damage affecting FPGA internal logic? Has someone encountered the similar problem in your project? How do you locate the broken part and pull FPGA back to work ? This chip is really expensive :(
10-13-2018 04:05 AM
Without knowing exactly what has caused the damage, it's impossible to say how much of the chip has been damaged.
If B33 and B34 are not working just because the VCCIO regulator for those two banks has failed (and is now outputting 0V), that should not damage the chip. As far as I know it's absolutely safe to run the chip with VCCIO = 0V on unused banks.
On the other hand, if the chip was damaged by ESD then it could be anywhere from "one pin not working" to "short circuit from VCC to GND".
Standard troubleshooting would be:
(1) Load the same bitstream onto an identical board, just to be sure that it is a hardware problem. If the new board does the same thing, it's not hardware-related.
(2) Put a multimeter on each of the power rails, the reset line, the DONE line, boot mode pins etc. Check that those are all reasonable.
(3) Repeat (2) with an oscilloscope to check for noise. Also put the oscilloscope on the data lines between the configuration ROM and the FPGA, to check what the configuration data looks like (ie nice square wave? Constant zero?)
(4) If all your power supplies look good and the chip isn't being held in reset, then you have a problem. If the bitstream is not being loaded from the PROM (eg. no clock output from the FPGA) then there's not much you can do; the chip is dead. If the bitstream is being loaded and you're not getting a DONE output, then the bitstream is most likely incorrect for the chip. If the bitstream is being loaded and the FPGA reports DONE, but there's nothing else happening, then maybe try generating a whole new super-basic bitstream for testing.