How to boost confidence level while implementing ?

[biks]

Hello all,

I am implementing some of my project on ZedBoard FPGA. Although I am able to implement on FPGA without any sort of error the confidence level of the design is showing "medium". I have already resolved all the clocking related activities. Please help me how to boost confidence level of design "high". (how to resolve internal node activity and I/O activity). Screenshot is added. 

[johnvivm]

You have the answer there:

- Specify your inputs (LVCMOS, TTL, LVDS, etc. also drive strength)

- Specify internal nets (especially clock frequencies)