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biks
Observer
Observer
498 Views
Registered: ‎12-22-2017

How to boost confidence level while implementing ?

Hello all,

I am implementing some of my project on ZedBoard FPGA. Although I am able to implement on FPGA without any sort of error the confidence level of the design is showing "medium". I have already resolved all the clocking related activities. Please help me how to boost confidence level of design "high". (how to resolve internal node activity and I/O activity). Screenshot is added. 

querry_1.png

 

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johnvivm
Voyager
Voyager
473 Views
Registered: ‎08-16-2018

You have the answer there:

- Specify your inputs (LVCMOS, TTL, LVDS, etc. also drive strength)

- Specify internal nets (especially clock frequencies)

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