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Explorer
Explorer
8,742 Views
Registered: ‎02-27-2018

How to convert LVDS input in a signal used in FPGA

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Hello,

 

I am using LVDS signals that have to be deserialized by an FPGA, how do i convert the LVDS signals into a single one that can be interpretated by the FPGA?

Do all the FPGA support this type of conversions?

 

Thank you

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Participant
Participant
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Registered: ‎02-11-2015

@lebowski, do you mean convert from differential to single?

Easiest way is with with buffer IBUFDS:

 

1. Add library of primitives

library unisim;
use unisim.vcomponents.all;

2. Instatiate the buffer

i_buffer : IBUFDS
port map (
   O => single_input,
   I => diff_input_p,
   IB => diff_input_n
);

 3. Enjoy your single signal.

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Scholar
Scholar
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Registered: ‎03-22-2016

@lebowski The simple answer is - you can use either a utility buffer (figure 1) or even clocking wizard (figure 2). ]

However there is way more than clock convention to worry about (jitter, frequency, etc) where these solutions would not be appropriate.

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ibufds_gte.png
clock_wizard_differential.png
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Participant
Participant
9,511 Views
Registered: ‎02-11-2015

@lebowski, do you mean convert from differential to single?

Easiest way is with with buffer IBUFDS:

 

1. Add library of primitives

library unisim;
use unisim.vcomponents.all;

2. Instatiate the buffer

i_buffer : IBUFDS
port map (
   O => single_input,
   I => diff_input_p,
   IB => diff_input_n
);

 3. Enjoy your single signal.

View solution in original post

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Explorer
Explorer
8,678 Views
Registered: ‎02-27-2018

Yes that is exactly what i meant, is single_input a std_logic?

I'm trying to find the source code for IBUFDS but i can't find it

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Explorer
Explorer
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Registered: ‎02-27-2018

Do all FPGA's have these kind of input pins?

I will have to work with 42 differential pairs and i have to choose the right FPGA with enough LVDS supported input pins.

I have also been reading that there were different LVDS standards (LVDS or LVDS_25 depending on the alimentation i guess)

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Contributor
Contributor
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Registered: ‎10-03-2016

If these LVDS pairs come from ADC, you have to choose the termination as true and as well as IOSTANDARD as LVDS_25. You can find the IBUFDS buffer template in language template in the tool.

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Participant
Participant
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Registered: ‎02-11-2015

All FPGAs with differential ports, at last 7-series. There are two standards supported: LVDS (1.8 V) and LVDS_25 (2.5 V), you can read details here:

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf page 91: "LVDS and LVDS_25 (Low Voltage Differential Signaling) ".

 

And path to the library with IBUFDS: C:\Xilinx\Vivado\<version>\data\vhdl\src\unisims\unisim_VCOMP.vhd. Type of port is "std_ulogic". You don't need to convert anything because "std_logic" is a subtype of "std_ulogic".

 

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Explorer
Explorer
8,647 Views
Registered: ‎02-27-2018

My LVDS pairs signals are the outputs of a LM98640 and in the DATASHEET of this component it is written that the supply voltage of the LM98640:

Supply Voltages: – 3.3V Nominal (3.15V to 3.45V Range)

                           – 1.8V Nominal (1.7V to 1.9V Range)

Does this mean i can't use the LVDS_25 standard, it seems that the SPARATN 7 supports only the LVDS_25 standard so i can't use the SPARTAN 7 if i understood it right?

I'm not sure that i'm looking at the right thing

lvds electrical.png
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Participant
Participant
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Registered: ‎02-11-2015

Right, Spartan-7 has only HR banks, therefore supports only LVDS_25.

But if you want to use only inputs (to FPGA), then you can use different VCC of the signals, and you need to disable internal resistors (DIFF_TERM = FALSE) and add exterenal termination resistors for them.

Read this case:

https://forums.xilinx.com/t5/7-Series-FPGAs/Generating-differential-output-from-Artix-7-HR-IO-bank-with/td-p/776282

and this:

https://www.xilinx.com/support/answers/43989.html

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Explorer
Explorer
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Registered: ‎02-27-2018

In fact i'm using only the inputs (to the FPGA) I'm trying to connect the LVDS outputs of a LM98640 to an FPGA, i've read the xilinx.com/support/answers/43989.html and for example for the diagram of the LVDS_25 standard, for the branch input i need to check VCCO VID VICM VOCM VOD but i'm not sure to which component these voltages refer to? to the FPGA or to the LM98640? In the datasheet of the LM98640 there are two supply voltages of 3,3 V and 1.8V and the differential output voltages of the LVDS outputs are from 275mV to 590 mV.

I don't really see anything else refering to VCCO VID VICM VOCM in the the LM98640

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Adventurer
Adventurer
4,041 Views
Registered: ‎06-05-2015
The below link will show you how to instantiate almost all buffers available in the FPGA.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf
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