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241 Views
Registered: ‎06-08-2019

How to generate SPI protocols already present inside Processing system ?

Hello,
We are trying to generate the SPI protocols signals from the Zybo-Z710 board, which uses Zynq-7000 SoC. Since, the PS section of the chip contains two SPI modules. Can anyone tells me the procedure for activating the SPI line inside the PS.
I want to use this SPI lines to transfer data and provide control to the another module.

Thanks

AMOL 

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4 Replies
Scholar drjohnsmith
Scholar
223 Views
Registered: ‎07-09-2009

Re: How to generate SPI protocols already present inside Processing system ?



Basicaly , you need to instantiate from the tools the SPI you want to use, and ensure those pins on your board are free for SPI,

Software wise, you instantiate the C routines that come when the IP is instantiated.

I'd guess, as you are asking this, you are new to configurable Processors like the Zynq. Once you have done a few setups its fairly intuitive, till then its like swimming in syrup.

Can I suggest you work your way through these

https://www.avnet.com/opasdata/d120001/medias/docus/3/SILICA_Xilinx_Zynq_ZedBoard_Vivado_Workshop_ver1.0.pdf

https://www.xilinx.com/support/answers/69276.html

https://www.udemy.com/course/zynq-training-learn-zynq-7000-soc-device-on-microzed-fpga/
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217 Views
Registered: ‎06-08-2019

Re: How to generate SPI protocols already present inside Processing system ?

Thanks.

Is anythere need to use Petalinux application in this ?

 

Regards

AMOL

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Scholar drjohnsmith
Scholar
215 Views
Registered: ‎07-09-2009

Re: How to generate SPI protocols already present inside Processing system ?

You dont have to use an OS to run the Zynq,

you can also run it "bare metal , native C coode

https://www.xilinx.com/support/documentation/application_notes/xapp1079-amp-bare-metal-cortex-a9.pdf
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203 Views
Registered: ‎06-08-2019

Re: How to generate SPI protocols already present inside Processing system ?

Thanks.

Ok!  Last question. I Made all the SPI as exetrnal interfaces. Can you how to connect it to the EMIO pins.

like this..Screenshot (7).png

I am using Viavdo 2019, my block diagram is looking like thisScreenshot (8).png

 

Thanks

Amol

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