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Visitor m.bahaidarah
Visitor
924 Views
Registered: ‎06-06-2018

How to implement IOSERDES using Vivado?

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Hello everyone, 

 

I'm using Spartan 7 - Arty board (XC7S50) to implement IOSERDES block as shown in the attachment on Vivado. The problem is that this is my first time dealing with Vivado and I couldn't find any idea on how to implement it by using IP blocks.

The idea of my design is to enter 12 bits (000000111111) parallel input to (OSERDES) in DDR mode and then, 2 outputs (serialized data and clock) will be connected to (ISERDES) in DDR mode in order to generate again the same parallel input. A check module will be added to check if the received value after applying some delay is the same (000000111111) or not, and according to that, it will generate a signal to the BitSlip in the ISERDES to correct the output.

 

I have read some Xilinx documents but it was not obvious how to start implementing that. Also, I'm struggling with finding some tutorials to explain this step by step.

So, could you please help me in detail if possible on how to implement this design? and if I have to insert some blocks (e.g. for the delay)? and how to convert the final blocks to Verilog code?

 

I appreciate any help and sorry for the long post.

Thank you in advance.

 

IOSERDES_BD.PNG
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Moderator
Moderator
1,032 Views
Registered: ‎04-18-2011

Re: How to implement IOSERDES using Vivado?

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Hi
That's no problem, everyone is learning all the time.
Did you take a look at The IO user guide
All these blocks are described in detail

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
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Moderator
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Registered: ‎04-18-2011

Re: How to implement IOSERDES using Vivado?

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you should take a look at XAPP585. 

This shows a 7:1 interface using the ISEDRES and it has an example of bitslip. 

 

http://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

 

 

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Visitor m.bahaidarah
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Registered: ‎06-06-2018

Re: How to implement IOSERDES using Vivado?

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Thank you Klumsde for your reply.

 

It's a helpful document where it contains some Verilog code, but I'm wondering if there is a simpler way to explain the relationship between ISERDES/OSERDES, ODELAY and PPL/MMCM.

I'm really sorry if what I'm asking is silly, but I'm still beginner and I need some help.

 

Thank you

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Moderator
Moderator
1,033 Views
Registered: ‎04-18-2011

Re: How to implement IOSERDES using Vivado?

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Hi
That's no problem, everyone is learning all the time.
Did you take a look at The IO user guide
All these blocks are described in detail

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Visitor m.bahaidarah
Visitor
789 Views
Registered: ‎06-06-2018

Re: How to implement IOSERDES using Vivado?

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Hi,

 

That document was very good. I have built the blocks and trying to integrate and test them.

Thank you.

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