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mengxiang1326725
Contributor
Contributor
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Registered: ‎11-18-2015

How to improve the warning or error level of vivado especially using verilog?

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Hello, everyone!

  I always use verilog. I found that the vivado won't tell you a critical warning or error that you don't declare the reg or wire but you use them in your program when you program with verilog. So, I just want to know if there is a way that made the vivado to tell you a error in the above case.

 Thanks!

Gu, Yue.

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pratham
Scholar
Scholar
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Registered: ‎06-05-2013

@mengxiang1326725 Yes, there is a way to do this using gui or tcl

 

Using tcl:

 

[BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_S_AXI_MEM_ID_WIDTH(4) on '/axi_emc_0' with propagated value(0). Command ignored

 

set_msg_config -id {BD 41-702} -new_severity {ERROR}

 

Just change the message ID with the Id number of warning/message which you wish to change to an error.  In the above example BD 41-702 is just a warning which would be changed to error after running above tcl command. 

-Pratham

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
can you give me example . I think vivado should give warning in above case
Thanks and Regards
Balkrishan
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pratham
Scholar
Scholar
7,575 Views
Registered: ‎06-05-2013

@mengxiang1326725 Yes, there is a way to do this using gui or tcl

 

Using tcl:

 

[BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_S_AXI_MEM_ID_WIDTH(4) on '/axi_emc_0' with propagated value(0). Command ignored

 

set_msg_config -id {BD 41-702} -new_severity {ERROR}

 

Just change the message ID with the Id number of warning/message which you wish to change to an error.  In the above example BD 41-702 is just a warning which would be changed to error after running above tcl command. 

-Pratham

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balkris
Xilinx Employee
Xilinx Employee
5,503 Views
Registered: ‎08-01-2008
To change the severity of a particular message, use the Tcl command "set_msg_severity".

Type "set_msg_severity -help" in the Tcl console or in a Vivado Tcl shell to get the complete command description and syntax.

The possible severities for a message and their general definitions are:

ERROR - An ERROR condition implies an issue has been encountered which will render design results unusable and cannot be resolved without user intervention.

CRITICAL WARNING - A CRITICAL WARNING message indicates that certain input/constraints will either not be applied or are outside the best practices for a FPGA family. User action is strongly recommended.

Note: Since this is a two word value, it must be enclosed in {} or "".

WARNING - A WARNING message indicates that design results may be sub-optimal because constraints or specifications may not be applied as intended. User action may be taken or may be reserved.

INFO - An INFO message is the same as a STATUS message, but includes a severity and message ID tag. An INFO message includes a message ID to allow further investigation through answer records if needed.

STATUS - A STATUS message communicates general status of the process and feedback to the user regarding design processing. A STATUS message does not include a message ID.


Every message delivered by the tool has a unique global message ID that consists of an application sub-system code and a message identifier. This results in a message ID that looks like the following:

"Common 17-54"
"Netlist 29-28"
"Synth 8-3295"

Use this command to customize the message severity returned by the tool to specific levels appropriate to your usage.

Note: You can restore the message severity of a specific message ID to its original setting with the reset_msg_severity command.

Examples:

The following example reduces or downgrades the significance of message ID "Common 17-54" from a CRITICAL WARNING to a WARNING so that it causes less concern when encountered:

set_msg_severity "Common 17-54" WARNING

The following example elevates or upgrades a common INFO message to a Critical Warning:

set_msg_severity "Common 17-81" "CRITICAL WARNING"

The severity of a DRC check can be set using the set_property command.

Example: Run the below command in Tcl console of Vivado to set the severity of "NSTD-1" to Warning

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
5,502 Views
Registered: ‎08-01-2008
check these ARs as well
http://www.xilinx.com/support/answers/54799.html
http://www.xilinx.com/support/answers/53034.html
Thanks and Regards
Balkrishan
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gszakacs
Instructor
Instructor
5,484 Views
Registered: ‎08-14-2007

If you don't declare a reg, you should gen an error if you make assignments to that reg in a process (always or initial block).  If you don't declare a wire, Verilog defaults to automatically declaring a (single) wire with that name.  You can override the default Verilog behavior using `default_nettype.  Note that this is a global switch like a macro definition, so to prevent issues with other code, you should reset it to the default at the end of your source file.  Example:

 

// Place outside of module

`default_nettype none

module foo

(

  input wire clk,  // inputs and outputs no longer have a default "wire" type, so you need to write it explicitly

  output reg Q,

  output wire bar

);

 

. . .

 

endmodule

// Outside module declaration, return default nettype to its default of "wire"

`default_nettype wire

 

-- Gabor