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Registered: ‎09-09-2019

How to instantiate IBUFDS in vhdl

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I'm working with a Xilinx Zynq-7000 SoC ZC702. Using the FMC connectors I connect differential signals (LVDS) to the zynq. I would like to have all the information on how to properly handle these signals in my project in vivado. If I understand correctly, I need to instantiate IBUFDS buffers in the top level file and connect the inputs of this buffer (I and IB) to the pins of the FMC connector and the O output is a single ended signal that I can use normally. I found this guide "ug953-vivado-7series-libraries" and the following code:

UNISIM Library;
use UNISIM.vcomponents.all;
- IBUFDS: Differential Input Buffer
- 7 Series
- Xilinx HDL Language Template, version 2018.3
IBUFDS_inst: IBUFDS
generic map (
DIFF_TERM => FALSE, - Differential Termination
IBUF_LOW_PWR => TRUE, - Low power (TRUE) vs. performance (FALSE) setting for referenced I / O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, - Buffer output
I => I, - Diff_p buffer input (connect directly to top-level port)
IB => IB - Diff_n input buffer (connect directly to top-level port)
);
- End of IBUFDS_inst instantiation

It's all new to me. I don't understand the meaning of these assignments. The above is the port map, but I imagine I need to declare this buffer as a normal component. Not knowing these attributes, I referred to ug953 and instantiated DIFF_TERM and IBUF_LOW_PWR as boolean type and IOSTANDARD as string.

Would it be possible to have larger code examples than the simple port map? Something in which we see in a complete manner how to use a buffer of this type in a complete project?

I would also appreciate any guide explaining how these buffers work or anything that can be useful in managing LVDS inputs.
Thanks,
Pietro

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Teacher
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Registered: ‎11-14-2011

Re: How to instantiate IBUFDS in vhdl

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You don't need to declare the component if you use the unisim.vcomponents.all library declaration.

The meaning of the generics and ports is clearly stated in UG953 (page 348 in my copy). I'm not quite sure what additional information you are looking for .. ?

The buffer is literally just that - it takes your differential LVDS signal and converts to a single ended signal to be used easily in your RTL design. No more special than that.

How to use them in a design? If you have an LVDS bus, you'll want to instantiate a number of buffers (possibly with a generate statement) to create a bus of single ended signals and use it as a usual vector in your RTL.

----------
"That which we must learn to do, we learn by doing." - Aristotle

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Teacher
Teacher
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Registered: ‎11-14-2011

Re: How to instantiate IBUFDS in vhdl

Jump to solution

You don't need to declare the component if you use the unisim.vcomponents.all library declaration.

The meaning of the generics and ports is clearly stated in UG953 (page 348 in my copy). I'm not quite sure what additional information you are looking for .. ?

The buffer is literally just that - it takes your differential LVDS signal and converts to a single ended signal to be used easily in your RTL design. No more special than that.

How to use them in a design? If you have an LVDS bus, you'll want to instantiate a number of buffers (possibly with a generate statement) to create a bus of single ended signals and use it as a usual vector in your RTL.

----------
"That which we must learn to do, we learn by doing." - Aristotle

View solution in original post

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