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thaus_015
Explorer
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Registered: ‎03-29-2017

How to match the lvds3.3v signal with lvds2.5v of Cyclone V FPGA board?

Hi,

 

I am using Kintex custom board [xc7k160tffg676-2] and Cyclone V FPGA board for one-way communication. I am trying to send lvds2.5v signal from Cyclone V FPGA board as input to lvds3.3v Kintex custom board. The grounds of the two boards are connected together. But i am unable to see any LVDS signals in ILA [Kintex custom board].

 

How to interface the lvds3.3v signal with lvds2.5v of Cyclone V FPGA board?Please suggest me ? 

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u4223374
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Registered: ‎04-26-2015

Have you got off-chip termination for the LVDS lines? The 7-series does not really have LVDS33 support like some older families did. They have LVDS25 support and that still works even if you power the I/O bank at 3.3V - but the on-chip LVDS termination does not work in this mode. If you want on-chip termination, you must power the I/O bank at 2.5V.

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tenzinc
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Registered: ‎09-18-2014

Thaus_015,

 

One of the mantra's here if it's not perfectly clear from the data sheet itself is to just run a quick point to point ibis simulation modeling the proper IO buffers for each part. If you want to be on the safe end I always suggest making sure you are using a external differential termination. Not only is it needed for VCCOs other than the one specced for the LVDS IOSTANDARD but generally it should also more precise over PVT than DIFF_TERM. 

 

Regards,

Tezz

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thaus_015
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Registered: ‎03-29-2017

Hi,

   Thanks for your response. How to create IBIS simulation model ? The below steps are i need to follow. Please explain me

To Generate an IBIS Model

     In the Design panel, select Implementation from the Design View drop-down  list. Image
     In the Hierarchy pane, select the top module Image.
     In the Processes pane, expand Implement Design.
     Do one of the following:
         For an FPGA design, expand Place & Route.
         For a CPLD design, and expand Optional Implementation Tools.
     Optional. Right-click the Generate IBIS Model process, and select Process Properties to set the IBIS Model Generation Properties.
     Double-click Generate IBIS Model. 
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gnarahar
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Registered: ‎07-23-2015

@thaus_015 Check this IBIS Model Generation guide from UG899 

You haven't though answered the query asked above if you have a 100 ohm external termination on your Kintex board? Can you share that information or show the schematic section of this part?

- Giri
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thaus_015
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Registered: ‎03-29-2017

we have not mounted differential termination resistors externally instead we using the following command

set_property DIFF_TERM TRUE [get_ports {}]
cons.GIF
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gnarahar
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Registered: ‎07-23-2015

@thaus_015 Is the bank VCCO 2.5V? If not, setting DIFF_TERM on a non-2.5V Bank is unsupported configuration for LVDS_25 IO Std. 

- Giri
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Keep conversing, give Kudos and Accept Solution when you get one.
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thaus_015
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Registered: ‎03-29-2017

Yes, 2.5 V only.

 

trigger pin [KINTEX custom board] is 3.3 v

 

But Trigger pin [Cyclone V FPGA board ] is 2.5 V [I/o} standard

 

LVDS.GIF
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thaus_015
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Registered: ‎03-29-2017

I need to pass LVDS signals of Cyclone V FPGA board  to LVDS input of KINTEX custom board.

 

I/0 Standard(LVDS) of Cyclone V FPGA board is LVDS

I/O Standard (LVDS) of KINTEX custom board i LVDS and LVDS_25

 

How to interface I/O standard of Cyclone V FPGA board to I/O standard of KINTEX custom board ? Please anyone suggest me ?

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thaus_015
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Registered: ‎03-29-2017

Have you got off-chip termination for the LVDS lines? yes

we have not mounted differential termination resistors externally instead we using the following command

                       set_property DIFF_TERM TRUE [get_ports {}]

 

I am working with KINTEX custom board [DAQ] : I/O standard [LVDS] is LVDS and LVDS_25

 

and Cyclone V FPGA board :I/O standard [LVDS] is LVDS.

 

 

LVDS.GIF

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bruce_karaffa
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Registered: ‎06-21-2017

@thaus_015

 

You need to answer @gnarahar's question.  What is the voltage connected to VCCO on the banks that you are using to receive the LVDS?

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thaus_015
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Registered: ‎03-29-2017

Please look_over the attachment.

 

2.5 V and 1.8 v for LVDS

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gnarahar
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Registered: ‎07-23-2015

@thaus_015 I believe we need to get a few things clarified here as I am a bit confused from some of the information you posted in the last 2 responses

 

  1. Can you explain what the trigger signal does in this interface? 
  2. It is a LVCMOS25 signal from the Cyclone connected to LVCMOS33 input on Kintex ?(from your I/O tab it is LVCMOS33 on Kintex) 
  3. Can you share your XDC file? 
  4. What is the VCCO Bank voltage on the board for bank 14, 15, 16, 32? I am not referring to the I/O Port tab shown value but what is actually provided on your board. Can you share the schematic that shows the VCCO voltages of  these banks? 
  5. How are you connecting the 2 boards? 
  6. You mentioned you don't see the LVDS signals in the ILA. Can you probe them externally and check if you are receiving the signals at the Kintex side and share those scopeshots? 
- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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thaus_015
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Registered: ‎03-29-2017

1  I am sending trigger signal From Cyclone V board to Kintex custom board. For every 500ns, trigger signal will be high/on-time.
   
2.  Trigger Pin [Cyclone Fpga] =I/O standard 2.5v
    clock_50 {cyclone FPGA] = I/O standard 2.5v
    LVDS Ports=I/O standard is LVDS
  
4 How are you connecting the 2 boards? Through Flat ribbon cable

 

 

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thaus_015
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Registered: ‎03-29-2017

>>Can you probe them externally and check if you are receiving the signals at the Kintex side and share those scopeshots? 

 

at the Kintex side, externally i probe the signals i am getting the signals only at pin which has LVDS I/O standard but not at the pins which have LVDS_25 I/O standard.

 

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