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hallovipin
Visitor
Visitor
17,719 Views
Registered: ‎06-15-2010

How to use core generated Block Ram in Verilog Code

Hello friends,

 

This may sound silly, but I am just starting using ISE. I have generated block RAM via ISE core generator module and added that to my code. Now How do I use the block ram? I mean core generator module is such that:

 

int_RAM RAM(

.clka(clk),

.ena(enable),

.wea(write_enable),

.addra(address),

.dina(in_dat),

.douta(out_data));

 

Now can you please tell me how to use it suppose I want to fill it with ADC data and thaen read it with above given signals.

 

thanx

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8 Replies
bassman59
Historian
Historian
17,700 Views
Registered: ‎02-25-2008

 


@hallovipin wrote:

Hello friends,

 

This may sound silly, but I am just starting using ISE. I have generated block RAM via ISE core generator module and added that to my code. Now How do I use the block ram? I mean core generator module is such that:

 

int_RAM RAM(

.clka(clk),

.ena(enable),

.wea(write_enable),

.addra(address),

.dina(in_dat),

.douta(out_data));

 

Now can you please tell me how to use it suppose I want to fill it with ADC data and thaen read it with above given signals.

 

thanx


 

You're asking us to do your design.

 

This is called "engineering."

 

It's not that difficult.

----------------------------Yes, I do this for a living.
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hallovipin
Visitor
Visitor
17,682 Views
Registered: ‎06-15-2010

@bassman

 

thanx for replying..

I am not asking to do my design...I am requesting to tell that how to proceed for read and write? DO I have to play with address only or I need to look after control signals also, as we do while writing HDL code to generate block memory instead of using a core generator IP.  

 

Your one line answer can make my day.:smileyhappy:

 

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eugen86
Observer
Observer
17,401 Views
Registered: ‎04-06-2009

HI, how to use the BRAM IP Core and a description of the signals is given by the Datasheet of the BLock Memory IP Core. Just click customize in COre Generator and on the botten left click Datasheet.

 

If write enable (WE) is high, the data at DIN will be written in the adressed memory.

 

 

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eteam00
Professor
Professor
17,398 Views
Registered: ‎07-21-2009

Seriously, you should not be particularly proud that you didn't check the design docs at the product web page.  It's not like Xilinx is hiding this stuff (Spartan 6 - Spartan 3a - Spartan 3e - Spartan 3) from you!

 

Or you might just use the website SEARCH box near the top right corner of the web page.

 

Or you could google the subject.

 

bassman isn't paid for helping out folks who post in these forums after beating their heads against a wall on frustrating problems (and neither do I, but that's based on what my advice is worth).

 

Some of the traffic in these forums comes from somewhat clueless students who don't understand how you can 'read' a register that is 'empty'.  Some of the traffic comes from SW developers who think they can design an FPGA in C code, without any fundamental understanding of hardware design.  Some of the traffic is from inexperienced designers (or wannabe designers) who think these forums are a free design service or engineering school (ex: I just bought a Spartan 3 starter kit, what is the first step to design an HD video processor?).  Then there are the reasonably competent designers who are clever enough to find the Xilinx website, find the support forums, find the appropriate support forum -- but somehow the value of looking up the manuals and guides, for the product or tool they are using, completely eludes them.

 

When you post a single question in this forum and you get a (supposedly straight) answer, you've learned the answer to your one question (and little more).  When you search the forums for answers, or search the website for the design docs, you get the answer to your question plus the answers to (hopefully) all the other questions you haven't yet answered.  What I don't get is this: why would anyone settle for so little information when there is so much information so readily available?

 

Thank you for allowing me to vent, apologies that you had to suffer the humiliation of my wandering rant (chalk that up to a grumpy mood and your unfortunate timing), and I hope I haven't chased you off.  On the other hand, if I've directed you to the materials you can use to be more knowledgeable, self-sufficient, and self-confident -- then maybe I've done a good thing.  We really can be nice folks occasionally (yes, even me).  Hopefully I don't get banned by Xilinx for chasing customers away.

 

-- Bob Elkind

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beep7886
Visitor
Visitor
14,690 Views
Registered: ‎06-11-2013

WOW... BASSMAN, why even say anything.  The question was not "do my design for me".  The whole point of this discussion board is to help eachother instead of posting lame comments like "This is called engineering".

You are zero help, and you rprobably don't even know what you are talking about anyways... you suck bassman, stick to fishing 

 

 

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bassman59
Historian
Historian
14,679 Views
Registered: ‎02-25-2008


@beep7886 wrote:

WOW... BASSMAN, why even say anything.  The question was not "do my design for me".  The whole point of this discussion board is to help eachother instead of posting lame comments like "This is called engineering".

You are zero help, and you rprobably don't even know what you are talking about anyways... you suck bassman, stick to fishing 

 

 


Well, if you want to bitch and moan about posts from almost THREE YEARS AGO, have at it.

Thank you for your concern, though.

Good luck in your career slinging burgers, because you won't last two days as an engineer.

----------------------------Yes, I do this for a living.
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umar.techboy
Newbie
Newbie
3,372 Views
Registered: ‎05-08-2018

Can we stop antagonizing the beginners in this forum? We had enough of it.

I've tried many, MANY approaches but in vein. After reading the docs carefully, especially THIS ONE, I've learned somethings. I created the Core with the following parameters:

Byte Write: Enabled,

Write/Read Width: 32,

Write Depth: 16000 (Its a Virtex-5 VLX50T)
Mode: Write First

Following is the approach:

Run system at 100MHz (signal clk in the code), generate separate Clock for Block Mem (signal BM_CLK) in the code. Run in case structures.

 

C0. Write Address=A0, DataIN=VAL_A, WEA=15 (All High) to write VAL_A on A0

C1. Give High BM_CLK edge in next cycle (BM_CLK=1)

6: bring back BM_CLK to 0, write Address=A1, DataIN=VAL_B, WEA=15 to write VAL_B on A1

7: Give High BM_CLK edge in next cycle

8: bring back BM_CLK to 0 and write Address=A0, WEA=0 (All Low). This address corresponds to VAL_0, right?

9. Give High BM_CLK edge in next cycle

10: bring back BM_CLK to 0 and read the Data from DOUT. This should read VAL_A, right??? but it doesn't!!!!
It always reads VAL_1 even in next cycles.

Here is the code for reference.
always @(posedge clk) begin
if (step == 0) begin
Address_BM <= 3;
WriteBuffer_BM = 32'hFFFFFFFF;
WE_BM <= 15;
step <= 1;
end if (step == 1) begin
BM_CLK <= 1;
step <= 2;
end else if (step == 2) begin
BM_CLK <= 0;
Address_BM <= 0;
WriteBuffer_BM = 32'hAAAAAAAA;
WE_BM <= 15;
step <= 3;
end else if (step == 3) begin
BM_CLK <= 1;
step <= 5;
end else if (step == 5) begin
BM_CLK <= 0;
Address_BM <= 3;
WE_BM <= 0;
step <= 7;
end else if (step == 7) begin
BM_CLK <= 1;
step <= 8;
end else if (step == 8) begin
BM_CLK <= 0;
outReg = Data_BM[15:8];
end

 

end

 

 

Can someone point out what exactly am I missing?

 

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jheslip
Xilinx Employee
Xilinx Employee
3,363 Views
Registered: ‎06-30-2010

a couple of things, as this is V5 I will move this to the Virtex board, also the original post was stale I would recommend starting a new post.

Also if this is a simulation issue show a screenshot of the issue.
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