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l19961106
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Registered: ‎10-30-2018

How to verify that oddr output is correct with fpga

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How to verify that oddr output is correct with fpga

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bruce_karaffa
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Registered: ‎06-21-2017

You will need to look at the output with an oscilloscope.  Since the ODDR is in the output tile, you can't use an ILA or any other internal mechanism to monitor the ODDR.  You can use an ILA to look at the data inputs to the ODDR.  If they are correct, the ODDR output should be OK logically.  The issues would be things like poor signal integrity caused by things like long unterminated traces. 

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bruce_karaffa
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Registered: ‎06-21-2017

You will need to look at the output with an oscilloscope.  Since the ODDR is in the output tile, you can't use an ILA or any other internal mechanism to monitor the ODDR.  You can use an ILA to look at the data inputs to the ODDR.  If they are correct, the ODDR output should be OK logically.  The issues would be things like poor signal integrity caused by things like long unterminated traces. 

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dpaul24
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Registered: ‎08-07-2014

@l19961106 ,

Apart from the above, you only other option is to have a GOOD simulation model where you can observe the ODDR outputs in the wave window.

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l19961106
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Registered: ‎10-30-2018

My oddr output is sometimes wrong, now I want to know it's the wrong time, and then automatically modify it through fpga, what's the way?

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l19961106
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Registered: ‎10-30-2018

My oddr output is sometimes wrong, now I want to know it's the wrong time, and then automatically modify it through fpga, what's the way?

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bruce_karaffa
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Registered: ‎06-21-2017

This should probably be a new post.  You need to tell us why it is wrong.  Use screenshots of the scope, ILA waveforms of the data going into the ODDR, the code related to the ODDR and why what you are seeing does not match what you are expecting.  Also tell us what board you are using and what IO standard is on these pins and how is the signal terminated on the receiving end.

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