04-08-2018 07:00 PM
I'm trying to figure out wiring of ZYNQ but I cannot find answer. I'd assume before POR signal is deasserted I can have connected I/O pins even if they technically exceed VIH as VCCO at this stage is 0. Is it correct or do I need to ensure that VCCO is up before any I/O can happen?
04-08-2018 11:55 PM
You have signals connected to a chip, the chip has gnd but no power, and the signals are driven ( have voltage on ) ?
If so this is the clasic, board inserted into a live backplane problem.
Technical answer is, it depends upon the current into each pin,
if its uA , then no problem, if it A, then problem, if its mA , then may be, depends how long for.
what your doing is heating the pins with the current.
Either way, not good design practise to have un powered chips driven , unless they say they can be, like some buffer chips.
At any board power up, you have the same problem, some parts will come up before others.
the 'answer' then is that its very transient, not 'that' high and current limited as the driving end is also coming up, so the heating is very limited.
All depends upon what time period your talking to drive the inputs with no power on the chip.
04-21-2018 01:24 PM
Thanks and sorry for the delay.
I'm still figuring things out the power on sequence - VCCO should be powered concurrently (or before) the external chips are powered (approximately).
That said for my benefit - I would assume most I/O is closer to voltage source than current source so it would depend on 'resistance' of the pins - if pin is connected to a MOSFET gate or to op-amp input I would expect current to be approximately 0 (sorry I have limited knowledge about VLSI and I'm still on 'discovering what I don't know' phase).
04-22-2018 01:53 AM
Can I suggest how to look at this.
I'd suggest that from a practical perspective , what causes the damage ?
If its heat, then your looking at Power, current and resistance and time
If its "ion" migration, then its voltage and time thats important.