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Visitor euy.choi
Visitor
7,308 Views
Registered: ‎06-29-2014

I cant see ODELAY2 delay in nc verilog simulation

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Since it is a vilinx primitive, I think maybe it is normal but I am not sure about that.

My current status is

I am making a test image that delays a signal. with a simple low to high transition. To find out If I can control the fixed delay of ODELAY2 and use it for other signals. Also check stability.

 

set_property LOC {AU30} [get_ports {delsig}]
IODELAY_GROUP <DELTA1>
//////XDC

 

assign ODATAIN =undelsig; //low to high signal input

odelay2 #(
.CINVCTRL_SEL("FALSE")
.DELAYSRC....(ODATAIN)
.HIGH_PERF..("FALSE")
.ODELAYTYPE ("FIXED")
.OdelayValue (31) //Also tried 0
.PIPESEL ("FALSE")
.REFCLKFREQ (200)
.SIGNAL PATTERN("DATA")
)
ODELAY2_inst (
.CNTVALOUT(CNTVALOUT)
.DATAOUT(delsig) //delayed output
.C(SYSCLK)
.CE()
.CINVCTRL(CINVCTRL)
.CLKIN()
.CNTVALUEIN()
.INC()
.LD()
.LDIPIPEEN()
.ODATAIN(ODATAIN)
.REGSRST(SYSRESET)
);

IDELAYCTRL IDELAYCTRL_inst(
.RDY(RDY) //This one I dont know where it goes
.REFCLK(REFCLK)//Something 200Mhz
.RST(SYSRESET)
);
//SYSCLK, SYSRESET added

In simulation, the delsig is delayed by 0.0006ns for both OdelayValue (31) and (0). Is this just because simulation cant show? Or some other reason?

 

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Moderator
Moderator
8,386 Views
Registered: ‎01-16-2013

Re: I cant see ODELAY2 delay in nc verilog simulation

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Hello,

 

I guess there is lots of confusion and misunderstanding.

 

ISE 13.3 support for cadence IES10.2. 

So you can use cadence IES10.2 and aove version with ISE13.3.

 

Which Virtex device you are targeting?

As you posted this in 7series forums we thought you are using Vivado and asked you to try with XSIM.

But if you are using any device lower than 7 series then you cannot go with Vivado you have to use ISE and you can use ISE simulator i.e. ISIM.

Vivado only supports 7 series and above.

 

Thanks,

Yash

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16 Replies
Moderator
Moderator
7,302 Views
Registered: ‎01-16-2013

Re: I cant see ODELAY2 delay in nc verilog simulation

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Hello,

 

Which simulation you are looking for?

Is it possible to provide detail info using snapshot. also attach the test case.

 

Thanks,

Yash

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Visitor euy.choi
Visitor
7,297 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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 http://12.30.21.21:8080/edms/docview.jsp?DocID=090310cf83807312&SInfo=1B|MjAxNDA4MDUxNzMxNDc=|MDkwMzEwY2Y4MzgwNzMxMg==&BackFlag=T

 

I am not sure if others can see this link. But our secure program is blocking other pic uploads...

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Moderator
Moderator
7,295 Views
Registered: ‎01-16-2013

Re: I cant see ODELAY2 delay in nc verilog simulation

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Sorry... I am unable to see the above link.

--Yash
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Visitor euy.choi
Visitor
7,289 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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well. The question itself is does ODELAY2 work well on cadence ncverilog RTL simulation. If it does, then I have to re-simulate.

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Community Manager
Community Manager
7,282 Views
Registered: ‎07-23-2012

Re: I cant see ODELAY2 delay in nc verilog simulation

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Hi,

If you are using a supported simulator the you should be seeing the correct functionality.

Refer to table 2-2 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug973-vivado-release-notes-install-license.pdf for details on supported simulators with 2014.2.

Recompile the simulation libraries to see if it could resolve the issue.

Regards,
Krishna
-----------------------------------------------------------------------------------------------
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Visitor euy.choi
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7,267 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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Cadence Incisive
Enterprise Simulator
(IES) (12.2-016)

is available. And since I am using IES13.3...Then there is something wrong with my design.

Is there anything strange about ODELAY or DELACTRL?

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Visitor euy.choi
Visitor
7,253 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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Community Manager
Community Manager
7,249 Views
Registered: ‎07-23-2012

Re: I cant see ODELAY2 delay in nc verilog simulation

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Since you are not using a supported simulator, we can't guarantee the functionality in the simulation.

Can you please try to use a supported simulator like XSIM and see if the error still persists?

Regards,
Krishna
-----------------------------------------------------------------------------------------------
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Visitor euy.choi
Visitor
7,244 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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ISE 13.3 is not supported? Then I have no option but to check the output manually..

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Moderator
Moderator
5,533 Views
Registered: ‎01-16-2013

Re: I cant see ODELAY2 delay in nc verilog simulation

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Hello @euy.choi ,

 

Hey sorry for the wrong info. Cadence IES 13.3 is supported simulator.

Now i guess you did typo you said its "ISE13.3"  it should be IES.

 

Please check the simulation using Vivado simulator then you can confirm that where is the problem in your design or in simulator.

 

Thanks,

Yash

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Visitor euy.choi
Visitor
5,529 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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It is ISE.. So I guess I should try the vivado simulator. Never used it before though

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Moderator
Moderator
8,387 Views
Registered: ‎01-16-2013

Re: I cant see ODELAY2 delay in nc verilog simulation

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Hello,

 

I guess there is lots of confusion and misunderstanding.

 

ISE 13.3 support for cadence IES10.2. 

So you can use cadence IES10.2 and aove version with ISE13.3.

 

Which Virtex device you are targeting?

As you posted this in 7series forums we thought you are using Vivado and asked you to try with XSIM.

But if you are using any device lower than 7 series then you cannot go with Vivado you have to use ISE and you can use ISE simulator i.e. ISIM.

Vivado only supports 7 series and above.

 

Thanks,

Yash

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Visitor euy.choi
Visitor
5,521 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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http://www.samsung.net/wiseblog/main/log.do?blogId=95164&logId=4532388

 

the system is virtex7 2000T

 

So I tried the vivado simulation. in RTL. I cutted off all RTL except clock generator and ODELAY IDELAYCTRL etc.

BUT It shows the signals DEL_TMS, UNDEL TMS is just 1 not a toggle signal.(Oh I changed the signal source to FPGA_xnRESET. 0->1 toggle)

 

DEL TMS is supposed to be the delayed signal.

I only added the signals and RUN behavirol simulation. Maybe I should run something else?

 

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Visitor euy.choi
Visitor
5,515 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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Oh I already found the problem. ODATAIN was connected to too many wires. Now I see the delayed signal!

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Visitor euy.choi
Visitor
5,511 Views
Registered: ‎06-29-2014

Re: I cant see ODELAY2 delay in nc verilog simulation

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Can I ask one more question?

The ODLEAY delayed my signal for..

tap1   0.678ns

tap21 2.28ns

tap31 3.018ns

 

1tap is about 0.08ns.

How is the delay for 1tap decided? Just the ODELAYprimitive given spec?

Or other factors like SYSTEM CLK?

 

The SYSTEM CLK is 20MHZ and REFCLK is 200MHZ.

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Moderator
Moderator
5,494 Views
Registered: ‎01-16-2013

Re: I cant see ODELAY2 delay in nc verilog simulation

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Hello,

To know about Tap delay please refer:
http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf (Page # 28)

There is no fixed value.
You need to check for timing report and adjust your tap value accordingly.

Thanks,
Yash
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