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saikiran.k
Observer
Observer
1,351 Views
Registered: ‎09-26-2018

IBUF_INTERMDISABLE placing issue.

 

I got an errors

  • [Place 30-69] Instance design_1_wrapper_inst/design_1_i/mig_7series_0/u_design_1_mig_7series_0_2_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq/IBUF (IBUF_INTERMDISABLE) is unplaced after IO placer.
  • [Place 30-68] Instance design_1_wrapper_inst/design_1_i/mig_7series_0/u_design_1_mig_7series_0_2_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq/IBUF (IBUF_INTERMDISABLE) is not placed.

while implementing a design using Artix 7 series fpga (XC7A35T FGG484 -2).

The design consists of 

  • Microblaze                                      1 no.
  • EMC flash controller                       1 no
  • Ethernet subsystem                        2no
  • MIG controller 7 series                   1 no
  • Uartlite                                            1no
  • IIC controller                                   1no
  • AXI-stream fifo                                2no

Any ideas to solve this error.

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gin_xil
Adventurer
Adventurer
1,347 Views
Registered: ‎01-19-2018

@saikiran.k,

Any ideas to solve this error.

NO! Not enough info.

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saikiran.k
Observer
Observer
1,336 Views
Registered: ‎09-26-2018

I got below mentioned critical errors.

[Constraints 18-586] IO constraint DQS_BIAS with a setting of TRUE for cell design_1_wrapper_inst/design_1_i/mig_7series_0/u_design_1_mig_7series_0_2_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs will not be propagated through the buffer. The constraint should be associated with the top level port. ["D:/Projects/npol_cavfe.core.com/branches/saikiran/artix100t_trail1/a7100t_setup/a7100t_setup.runs/impl_1/.Xil/Vivado-19196-saikirank/dcp35/design_1_mig_7series_0_2.edf":120721]

[Constraints 18-586] IO constraint DQS_BIAS with a setting of TRUE for cell design_1_wrapper_inst/design_1_i/mig_7series_0/u_design_1_mig_7series_0_2_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs will not be propagated through the buffer. The constraint should be associated with the top level port. ["D:/Projects/npol_cavfe.core.com/branches/saikiran/artix100t_trail1/a7100t_setup/a7100t_setup.runs/impl_1/.Xil/Vivado-19196-saikirank/dcp35/design_1_mig_7series_0_2.edf":120729]
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saikiran.k
Observer
Observer
1,334 Views
Registered: ‎09-26-2018

we have generated our UCF file for DDR3 using ISE tools but we are trying to implement the design in the vivado 17.4 will this be the reason for causing this issue.
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