03-20-2021 08:11 PM - edited 03-20-2021 09:42 PM
We are capturing a LVDS bus in 7 series Zynq (z7020). We want to additionally pass the clock to ISERDES so that we can calibrate automatically and achieve centring.
Code used is,
) IBUFGDS_DIFF_OUT_inst (
1. At lower freq (30MHz, 40Mhz, 60Mhz) we see capture is good.
At 80 MHz and above capture has errors.
2. Board appears to be fine. We have purchased the board and it is supposed to work at much higher speeds.
1. The attached picture is an implementation schematic. The maco IBUFGDS_DIFF_OUT expands into two individual IBUFDS.
Will there be double termination on the pin ? i.e instead of 100 ohm termination, will the termination be effective 50 ohm ?
2. Same code works on ultrascale+ boards well. In Ultrascale+ IO I see only one DIFF element.
3. For 7 series FPGA is there a recommendation on how to connect the IBUFGDS_DIFF_OUT ?
Should I try a different macro ?
We need to derive two signals internally from the clock differential PIN. One signal should go to MMCM (we are passing it through IDELAY) and other signal should go to ISERDES (again we are passing it through another IDELAY). Though this connection is recommended in xapp585, I am not sure if this is correct. Please suggest.
03-25-2021 10:54 AM
In the snippet of code .IOSTANDARD("DEFAULT") so I think this will be LVDS_25. The termination is .DIFF_TERM("TRUE"), so you will get the 100ohm between the P and N pair.
It maybe that the issue is the with the clock/data alignment. How are you controlling the alignment?