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Observer
Observer
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Registered: ‎12-29-2015

ICAPE2 Vs JTAG issue

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Hi,
I am trying to design a system in my PL area of Zybo FPGA board. 

The system is intended to read-back the configuration memory after the bitstream loading completes and do some computation on the read data. 

 

I have read 7 Series FPGAs Configuration User Guide(UG470) and understood that I have to use the ICAPE2 primitive within my HDL code to achieve this. 

 

My confusions are the following:

1) Config mode pin M[2:0] should not be set to JTAG mode while using ICAP. Does it mean that I am not allowed to configure with JTAG in first place if I intend to use ICAP after configuration? or I can program using JTAG, but before start using the ICAP I should switch away from JTAG mode (by changing the config mode switches/jumpers)? 

 

Or I am required to program the bitstream with other techniques(QSPI or SD card) to begin with?

 

2) If I use a Xilinx Integrated Logic Analyzer (ILA) to observe the behavior, does that imply that I am using the JTAG resources? Does it further mean that by using the ILA for debug, I am preventing the operation of ICAP? Unfortunately  ILA is convenient and I am not sure what other output dumping mechanism is available that does not use the JTAG. 

 

 

3) To examine the first two points  I went ahead and Instantiated an ICAPE2 primitive in my Zybo board and implemented some simple modules along with that. I connected the ILA probes with the data out (signal: icap_data_reg_o), RDWR, and CSIB signal of the ICAPE2 instantiation. And tried to observe it. The RDWR and CSIB were connected to switches. I programmed with JTAG but after programming I switched the mode pin jumper to something else. 

 

I tried various values of RDWR and CSIB that should cause an ABORT. At-least that would allow me to know if the ICAP is functioning.  However I did not write anything on input bus. But the output I got does not represent ABORT status. The 32 bit ICAP output just stays in FFFF FF9b irrespective of what I provide as input to RDWR and CSIB.

 Here, the important bits are icap_data_reg_o[7:0]=1001 1011.   icap_data_reg_o[31:8] is high (see unnamed.png). 


Based on the ICAP output, could you suggest if the ICAP is functioning? I was trying to ensure that before writing the whole HDL code to readout the config bits. 

Thanks. 

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Scholar
Scholar
5,380 Views
Registered: ‎06-05-2013

Re: ICAPE2 Vs JTAG issue

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@tamzid #1 Change the mode pins to some other mode but not the JTAG mode. You can access the JTAG any time irrespective of mode pins.

 

#2 No you could use the ICAP with ILA and VIO cores without any issues.

Just make sure mode pins are not set to JTAG.

#37

http://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf

-Pratham

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Scholar
Scholar
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Registered: ‎06-05-2013

Re: ICAPE2 Vs JTAG issue

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@tamzid #1 Change the mode pins to some other mode but not the JTAG mode. You can access the JTAG any time irrespective of mode pins.

 

#2 No you could use the ICAP with ILA and VIO cores without any issues.

Just make sure mode pins are not set to JTAG.

#37

http://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf

-Pratham

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Observer
Observer
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Registered: ‎12-29-2015

Re: ICAPE2 Vs JTAG issue

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Hi pratham,
Thanks for your quick reply. Please see inline to help me clarify:

 

 

==>pratham: #37

http://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf

==>Tamzid:

Do you think a microblaze+AXI HWICAP would be easier to implement and debug compared to HDL FSM+ICAPE2 primitive for reading out the configuration memory?

 

I did not use MicroBlaze before in any of my design. Hence may need some extra effort to get started with that. But I am open to this option if that gives me significant benefit in debug and implementation. I understand that the overhead would be larger using MicroBlaze. But that is OK for now. 

 

 

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Scholar
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Registered: ‎06-05-2013

Re: ICAPE2 Vs JTAG issue

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Yes, I think microblaze with AXI HWICAP would be easier but it largely depends on the designer.
-Pratham

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