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Visitor d.a.vahlsing
Visitor
5,485 Views
Registered: ‎06-02-2014

IDELAYCTRL REFCLK_FREQUENCY

Hi all,

I'm wondering about the discrete nature of the given min/max values of 200/300 MHz for the ref clock of the IDELAYCTRL in DS182 (v2.8) March 4, 2014.

Having run some tests with different ref clks from 200 to 300 MHz on the KC705 eval board it looks like the IDELAYCTRL is quite happy being given any frequency in the 200 to 300MHz range. The measured ODELAY tap delays follow the given equation 1/(32 x 2 x FREF) [ps] nicely. The RDY signal gets asserted. Just some warnings remind to only use values in the 190-210MHz or 290-310MHz ranges for the REFCLK_FREQUENCY parameter of the ODELAYE2.

Increasing the ref clk in several steps up to 400MHz still worked without significant increase in jitter, although my measurements were kind of rough with regard to in detail jitter analysis.

For my application I do need some fine grained realtime controllable delay of up to several 100ns with a min resolution of about 50ps and an overall jitter of up to +/-30ps. Taking my observations into account there are 3 possible solutions:

1) use 1/(32 x 2 x 300.0MHz) = 52.038ps => this is according to spec, but ugly to use in the application
2) use 1/(32 x 2 x 312.5MHz) = 50.000ps => this is just beyond spec, but already nice to calculate in the application
3) use 1/(32 x 2 x 333.3MHz) = 46.875ps => this is 1/32th of 1.5ns, further beyond spec, but even much nicer to use in the application

Since even the finally targetted XC7K70T-2 device will be >80-90% empty and running in a tight climate controlled environment going slightly out-of-spec seems a viable approach. But to be able to judge my out-of-spec solutions it would be very helpful to get some hints on the amount of margin being included in the 310MHz max ref clk spec value or to get some functional insights into the IDELAYCTRL & ODELAYE2s.

Best regards,

Dirk

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2 Replies
Scholar dwisehart
Scholar
5,481 Views
Registered: ‎06-23-2013

Re: IDELAYCTRL REFCLK_FREQUENCY

We discussed this a while back in a different thread, though we were discussing going below 200 MHz at the time:

 

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/IDELAYE2-Ref-Clock-Freq-below-200-MHz/m-p/447230

 

This app-note is slightly dated, but it has a lot of good info on IDELAYCTRL all the same:

 

http://www.xilinx.com/support/documentation/application_notes/xapp707.pdf

 

Regards,

Daniel

 

Visitor d.a.vahlsing
Visitor
5,454 Views
Registered: ‎06-02-2014

Re: IDELAYCTRL REFCLK_FREQUENCY

Thnaks for directing me to the xapp707! That was real food compared to the many discussions on that topic ending quite open I had found so far!

So the remaining question is: how similar are the Series-7 delays to the analyzed Virtex-4 delays?

Regards,

Dirk
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