08-31-2017 02:27 AM
I'm having some troubles while debugging with Arty (Artix 7 FPGA).
I used ILA to debug my program on Zybo (Zynq) and Nexys 4 DDR (also Artix 7), and everything worked fine.
I used the same procedure as before to debug a slightly different program on the Arty board, with no success...
The message I receive when programming the bitstream into the FPGA:
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7a35t_0 and the probes file D:/Vivado_files/Arty_12960_FSM_ILA_2015/Arty_12960_FSM_ILA_2015.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.
I've tried the same procedure on both Vivado Design Suite 2015.4 and 2017.2.
I verified the programming was with the correct bitstream and probes file.
Is it possible the Arty does not support ILA debugging? I couldn't find anything on the net.
Thanks in advance!
08-31-2017 02:37 AM
check the steps given in warning message
The clock net connected to dbg_hub is automatically selected by the tool based on the debug core configuration and connections.
However, you can change this clock net by modifying the "connect_debug_port" command in XDC.
The following are possible causes and solutions:
1. The clock that is connected to dbg_hub is a non-free-running clock.
2. The clock is a free running clock but the signal integrity of this clock net is not good.
Check if the quality of this clock signal on the board is good or not. One example of this issue is if the daughter card connector is not inserted tightly (clock is coming from the daughter card).
3. Try the second solution mentioned in the warning message which is to use the other User Scan Chain number.
For example, the following are the steps to change to use Scan Chain number 2:
08-31-2017 05:10 AM
Thanks for the quick reply!
1. I'm not sure what is the exact definition of a free-running clock. I used the output clock from "clocking wizard" (clk_out1 in the attached diagram), and this is the same clock I've used in previous debugging on Zybo and Nexys (with success).
2. "Check if the quality of this clock signal on the board is good or not. One example of this issue is if the daughter card connector is not inserted tightly (clock is coming from the daughter card)."
This is a new board and I assume it is not damaged. Do you suggest to measure the clock with a scope?
3. I've done as suggested, but I'm not sure how to continue.
I understand I need to type the command BEFORE programming the device. But what should I do next?
After connecting manually with connect_hw_server, there is no option to program the device and it says the device is closed (second picture).
Notice the second warning:
"The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s)."
This is why I assumed there is a problem with debugging with Arty, it says the device design has 0 ILA cores (even though I followed the same procedure that worked for me before).
Thanks again for the help.