cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
13,419 Views
Registered: ‎02-08-2013

IN_FIFO demultiplexed bit order?

Jump to solution

Does anybody know the demultiplexed sample order of the IN_FIFO Q outputs when used in 4x8 mode?

 

ie. Is Qn[3..0] Sample 1 or 2?

 

Can't seem to find this key bit of info in the datasheet (ug741 v1.3).

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
15,771 Views
Registered: ‎02-08-2013

Yes my question was about the nibble order, thats what is not mentioned in the datasheet. It just says that in 4x8 mode the 4 bit input is demultiplexed to an 8-bit ouput. I would assume the first nibble was bits 0..3 but that wasn't the case with the general asymmetrical fifo that packs the smaller width input to the most significant end of the output!

 

So to confirm you are saying:

 

Q[3..0] = nibble 1, first sample of D

Q[7..4] = nibble 2, second sample of D

 

?

View solution in original post

0 Kudos
5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
13,412 Views
Registered: ‎10-11-2007

Are you asking how the ISERDES is connected to the IN_FIFO in 4x8? Then Q1 -> Dn<3>, Q2 -> Dn<2>, Q3 -> Dn<1> and Q4 -> Dn<0>.

Or  is it FIFO in to output data? Then its:

D0[3:0] maps to Q0[7:0],

D1[3:0] maps to Q1[7:0],

…………………

D9[3:0] maps to Q9[7:0]

 

But I think this is in the I/O user guide UG471

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
13,408 Views
Registered: ‎10-11-2007

Oh, I forgot. Firts nibble to MSB of the byte.

 

1st D[3:0]  -> Q[7:4]

2nd D[3:0 -> Q[3:0]

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
13,406 Views
Registered: ‎10-11-2007
Sorry, the other way around. Memory is fading
0 Kudos
Highlighted
Adventurer
Adventurer
15,772 Views
Registered: ‎02-08-2013

Yes my question was about the nibble order, thats what is not mentioned in the datasheet. It just says that in 4x8 mode the 4 bit input is demultiplexed to an 8-bit ouput. I would assume the first nibble was bits 0..3 but that wasn't the case with the general asymmetrical fifo that packs the smaller width input to the most significant end of the output!

 

So to confirm you are saying:

 

Q[3..0] = nibble 1, first sample of D

Q[7..4] = nibble 2, second sample of D

 

?

View solution in original post

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
13,385 Views
Registered: ‎10-11-2007
Yes.
0 Kudos