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Explorer
Explorer
1,885 Views
Registered: ‎01-13-2018

IO Standard for XADC

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Hi, 

I am trying to configure XADC on Z-Turn 7Z020. According to the Product User Manual of Z-Turn 7Z020 there is only one XADC channel which is routed to IO Pin Header. 

XADC_INP0 is connected to K9 of ZYNQ

XADC_INN0 connected to L10 of ZYNQ

In the Block Diagram of Vivado I made VauxP0 and VauxN0 external but I need to assign pins K9 and L10 in XDC constraint file with IO Standard, right ? Are they mapped to LVCMOS33 ? I don't find K9 and L10 in IO Planning tool in Vivado. 

 

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Registered: ‎01-22-2015

Re: IO Standard for XADC

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@joniengr081

   … but I don't need to make it external and assign IOSTANDARD to Xaux0 in XDC file, according to your reply, is that right ?

No. In the package file for your FPGA, you will find that the Xaux0 pins have names that look something like “IO_L1P_T0_AD0P_15”. The parts of this name are explained in Table 1-12 of UG475. This Table also identifies "dedicated” pins, for which you don’t need to set the IOSTANDARD.   The auxiliary inputs to the XADC (AD0P through AD15P, AD0N through AD15N) are “multifunction” pins, for which you must set the IOSTANDARD.

-but now things get a little confusing. As sandrao indicates, the section called “Auxiliary Analog Inputs” found on about page 29 of UG480 says “an IOSTANDARD must be selected that is compatible for the bank even though the IOSTANDARD does not affect the input programming.” This means that you can (and must) specify any IOSTANDARD for the multifunction Xaux0 pins that is compatible with VCCO for the FPGA bank containing Xaux0. For example, if VCCO=3.3V for the bank then you can use the IOSTANDARD of LVCMOS33 for each of the Xaux0 pins.

Mark

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Community Manager
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Registered: ‎08-08-2007

Re: IO Standard for XADC

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Hi @joniengr081,

For 7 Series you need to pick an IOSTANDARD that is compatible with the rest of the IOs in the bank.

When they are used at auxiliary inputs the IOSTANDARD is not actually applied to the pins but is required to get through the tools. Hence picking any standard that works with the other IO in the bank.

 

Sandy

 

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Explorer
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Registered: ‎01-13-2018

Re: IO Standard for XADC

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Thanks for reply but I am not sure if I understood it completely. XADC channel 0 (VauxP0 and VauxN0) is routed from BGA K9 and BGA L10 to Pin 5 and Pin 7 of 80 Pin Header on Z-Turn 7Z020 Board. Do I need to assign IO Standard for these two signals ? and assign them to K9 and L10 in Vivado IO Planning tool ? Is LVCMOS33 the right standard ? 

I am not able to find K9 and L10 when I select LVCMOS33 in IO Port Tool. There is only one option for Package Pin as shown in attachment. 

Untitled_02.png
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1,825 Views
Registered: ‎01-22-2015

Re: IO Standard for XADC

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@joniengr081

     I need to assign pins K9 and L10 in XDC constraint file with IO Standard, right ?
I think you are referring to dedicated analog inputs to the XADC.  If so, then there is no need to use "set_property IOSTANDARD" for these pins in the XDC constraints file.  The ZYNQ has other “dedicated pins” (for example, those associated with the configuration interface) that also do not need "set_property IOSTANDARD" constraints.

Mark

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Registered: ‎01-13-2018

Re: IO Standard for XADC

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Thanks. I understand this now. 

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Community Manager
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Registered: ‎08-08-2007

Re: IO Standard for XADC

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If you do not set the IOSTANDARD you will get a DRC error from Vivado. 

UG480 page 29 "In the Vivado design tools, an IOSTANDARD must be selected that is compatible for the bank even though the IOSTANDARD does not affect the input programming. All configuration is automatic when the analog inputs are connected to the top level of the design. Only those auxiliary inputs connected in a design are enabled as analog inputs"

This is different to the MIO pins on the Zynq 

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Explorer
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Registered: ‎01-13-2018

Re: IO Standard for XADC

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Hi, 

In XADC IP Core there are 17 auxiliary differential analog inputs (Xaux0 : Xaux16). I have to use Xaux0 because only this differential input is routed to 80 pin header in Z-Turn 7Z20 but I don't need to make it external and assign IOSTANDARD to Xaux0 in XDC file, according to your reply, is that right ?

But I don't why in Zybo XADC Demo Example they have defined them in XDC file. 

I able to generate bit stream without making them external but when I connect the analog signal to the analog pins there is no change in the ADC reading. 

 

 

Untitled_03.png
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Registered: ‎01-22-2015

Re: IO Standard for XADC

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@joniengr081

   … but I don't need to make it external and assign IOSTANDARD to Xaux0 in XDC file, according to your reply, is that right ?

No. In the package file for your FPGA, you will find that the Xaux0 pins have names that look something like “IO_L1P_T0_AD0P_15”. The parts of this name are explained in Table 1-12 of UG475. This Table also identifies "dedicated” pins, for which you don’t need to set the IOSTANDARD.   The auxiliary inputs to the XADC (AD0P through AD15P, AD0N through AD15N) are “multifunction” pins, for which you must set the IOSTANDARD.

-but now things get a little confusing. As sandrao indicates, the section called “Auxiliary Analog Inputs” found on about page 29 of UG480 says “an IOSTANDARD must be selected that is compatible for the bank even though the IOSTANDARD does not affect the input programming.” This means that you can (and must) specify any IOSTANDARD for the multifunction Xaux0 pins that is compatible with VCCO for the FPGA bank containing Xaux0. For example, if VCCO=3.3V for the bank then you can use the IOSTANDARD of LVCMOS33 for each of the Xaux0 pins.

Mark

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Explorer
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Registered: ‎01-13-2018

Re: IO Standard for XADC

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I am sorry for confusion.

Q1: If the XADC differential pins (Xaux0) are defined in Board Files then do I still need to make these pins external in Block Diagram at XADC IP and write correct IOSTANDARD for them in XDC ? 

Making external is shown in attachment. The bitstream can be generated without making them external even if the differential pins (Xaux0) are enabled in XADC IP

Q2: If the XADC differential pins (Xaux0) are NOT defined in Board Files then I have to make these pins external and write correct IOSTANDARD for them in XDC, is that right ?

Q3: I don't find the assignment of XADC differential pins (Xaux0) in Board Files. Therefore, I made them external and now trying to assign the signals to BGA pins with IOSTANDARD. Is that right what I am doing ? 

Untitled_06.png
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Registered: ‎01-22-2015

Re: IO Standard for XADC

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@joniengr081

I am not very familiar with Board Files. However, I understand from reading Appendix A of UG895 that they contain information that is normally found in the XDC constraints file.  So, if the Xaux0 pins are defined correctly in the Board File then you should not need to define them in the XDC file.

The XDC file constraints look similar to the following:

set_property PACKAGE_PIN G15 [get_ports vauxp0]
set_property PACKAGE_PIN G16 [get_ports vauxn0]
set_property IOSTANDARD LVCMOS33 [get_ports vauxp0]
set_property IOSTANDARD LVCMOS33 [get_ports vauxn0]

Reminders:

  1. Use the correct port names. I have used vauxp0 and and vauxn0, but your port names may be different.
  2. Use the correct FPGA pin IDs.  I have used G15 and G16, but your FPGA pin IDs may be different.
  3. CAUTION: Use the correct IOSTANDARD. I have used LVCMOS33, which is allowed if VCCO=3.3V for the FPGA bank containing vauxp0/vauxno. If VCCO does not equal 3.3V then you must use another IOSTANDARD.


Mark

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Registered: ‎01-13-2018

Re: IO Standard for XADC

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markg@prosensing.com and others.  

Thanks for replies.  

I have looked into the document of Z-Turn 7Z-020. It does not have any auxiliary analog channel connected. I am sorry for this confusion earlier in the post. 

It has only one dedicated analog channel (Vp/Vn) available at pin 5 and pin 7 of 80 pin connector for which we don't need any IOSTANDARD and package pin assignment in XDC file. This is the only XADC channel available for external analog signal on this board. 

I have enabled AXI interface in XADC wizard and have connected S_AXI of XADC to M_AXI_GP0 of ZYNQ PS through AXI interconnect. Then in SDK I read some internal parameters and also the dedicated analog channel (Vp/Vn). These reading are send to USB-UART. The readings of dedicated channel (Vp/Vn) matches with the external voltage.

The block diagram is available in attachment. I anyone interested I can also share the SDK file.    

 

Untitled_07.png
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Newbie seomotard02
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Registered: ‎11-19-2018

Re: IO Standard for XADC

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I really enjoyed.

 

เว็บแทงบอล  : po

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Registered: ‎01-30-2019

Re: IO Standard for XADC

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Hi joniengr081,

    Can you kindly attach your SDK file, for the block diagram you have attached.

 

 

Thankyou,

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