04-17-2019 11:31 PM
The VCCIO to an FPGA IO bank is the only thing that determines the output voltage of any of the pins in that bank.
During pin assignment/pin planning, we can configure the IO to be of a particular standard. I want to understand what is exactly being configured by the FPGA, if anything at all.
Consider that we supply VCCIO to bank 1 as 3.3v. What is the difference between setting the IO Standard as LVCMOS33 and LVTTL33?
Let's say we consider a pin from an input perspective, is there internal circuitry inside the IO stage that can actually split between these two different standards to discern between a digital '1' and digital '0'? (between LVCMOS and LVTTL is just a matter of different thresholds).
In addition, setting IO Standards affect timing closure? Does the timing analyzer take the IO standard into consideration?
04-18-2019 04:56 AM
Yes, there is internal circuitry that can change the thresholds and pin behaviour for each of the I/O standards. I don't think Xilinx ever provides a full diagram, but it's clear that each I/O pin has a substantial amount of circuitry associated with it.
As far as I know, the I/O standard does not affect timing closure. It's assumed that once the signal hits the I/O pin then Vivado has done its job, and everything past that (ie interaction of the I/O standard, voltage, and output drive strength with the PCB and the chip at the other end) is something that the user will figure out and specify as a timing requirement.
04-18-2019 09:37 AM
It's assumed that once the signal hits the I/O pin then Vivado has done its job, and everything past that (ie interaction of the I/O standard, voltage, and output drive strength with the PCB and the chip at the other end) is something that the user will figure out and specify as a timing requirement.
That's not entirely true.
Vivado does understand that different I/O standards will have different timing characteristics. However, @u4223374 is correct that the timing analysis that Vivado does is based on one set of system conditions (per I/O standard). If you look at the datasheet for your device (for example for Kintex-7 DS182), there is a section on "I/O Standard Adjustment Measurement Methodology" - in that section it outlines how the measurements are done, and hence the characteristics of the system for which the timing numbers provided are valid. Of particular interest (for outputs) is Table 24 which shoes the RREF and CREF assumed for the timing numbers (and note that CREF is 0 for almost all I/O standards).
A real system will have different system characteristics for the I/O. If you really need to know how these affect the timing analysis, then it is up to you to determine the derating required between the timing provided by Vivado and what you will see on your board. To do this, Xilinx supplies (under NDA) both IBIS and SPICE (I think) models for the I/O so that you can do analog simulations of your I/O.
04-18-2019 09:46 AM
IBIS provided by write_ibis (tcl) in Vivado, no NDA needed...
Hspice models do require NDA, and they are encrypted as well (licensed to Xilinx by TSMC, so no technology related information is visible).