01-19-2021 02:43 AM
While the maximum toggle rate of an IO register is probably listed in the data sheet (I don't have a copy handy), the practical IO rate is determined by a number of factors such as Select IO type (LVDS, LVCMOS33, etc), number of bits, interface type (source synchronous/system synchronous), clock jitter, board layout and a host of other things. You need to design the interface part of your code in Vivado and see if it meets timing.
01-19-2021 03:29 AM
To add to the previous reply we recommend performing an IBIS simulation so assess the HW performance. The IO Solution Center is a good reference to talk through the Performance implications.
01-19-2021 04:46 AM
I'm sorry for my bad expression.I really want to know is how to get the IO information of a device(such as xczu3eg).I need to determine whether the max IO speed can meet my design requirement or not.
01-20-2021 05:26 AM
In the DS there are some information on specific protocols like MIPI and DDR4, there is a table for LVDS examples as well.
But you will need to an IBIS simulation of your setup (your RX/TX and transmission line) so see what the max IO performance is for your scenario.
01-20-2021 05:56 AM
Io speed is determined by a few things,
What port on the device, some ports are High speed capable some low speed capable. depends upon the device.
next come the speed grade of the device, a -3 part will be faster than the -1 part for instance
then comes the logic standard you want to use. SSTL is faster than LVCMOS33
then it assumes you can use the IOB register directly on the IOB pin or is it an internal register, for fast do not use internal registers on the output.
Once you have selected these parameters, its all in the data sheet.
In reality , its much easier and more instructive to make a simple registered output counter say, force the output registers into the IOB with IOB=TRUE, and make some designs
you will then see in the reports the different clock to out speeds you get, and it will inform you as to how best to code your output logic.
01-20-2021 05:59 AM
There are a couple components to IO speed. Signal Integrity (SI) refers to the ability of the traces on your PCB to carry a signal of the frequency and voltage that you need. This may be modeled in an IBIS simulation as described by @sandrao . Another is the ability of the interface to meet timing. That is, can the clock and data be made line up in such a way that you can receive data without error. A third component is the ability of the input buffers and input registers to work at the frequency you need. Of these, the third may be the only item that can be only thing that can be given a firm number without analyzing you design and can be found in the data sheet for the device. It is however almost never the limiting factor. If you give us some idea of what you are trying to do, interface type (serial, parallel), IO standard, pin type (MGT, HP, HD), frequency, we might be able to help