02-03-2021 10:03 PM
I am using Select IO interface wizard (5.1) in virtex-7 (VX485tFFG1930) for ADC interface. I have instantiated it 8 times , Same Code I have done in ISE 14.7 and as well as Vivado 17.4 there is no issue but when i am migrating it to vivado 19.1 I am facing the following error
[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells 'ADC_FILES/Data_Capture_Clock_Process/ADC1_ch1_1/inst/delayctrl' and 'ADC_FILES/Data_Capture_Clock_Process/ADC1_ch1_2/inst/delayctrl' have same IODELAY_GROUP 'selectio_adc_group' but their REFCLK signals are different
Can anyone let me know what may be the solution. I have tried many possibilities by seeing the solutions in Xilinx forums but in vain.
Thanks & Regards,
02-05-2021 09:55 AM
Do you include the IDELAYCTRL in the SelectIO Wizard?
if you are instantiating the Wizard 8 times I would suggest deselecting this option and include one IDELAYCTRL at the toplevel. That will allow Vivado to replicate the IDELAYCTRLs and associate the correct IDELAYs.
Otherwise you need to create IODELAY_GROUP for each of the 8 instantiations grouping the delays with their IDELAYCTRL.
02-09-2021 12:39 AM
I have gone through one of the forum and added the following lines in the constraint file and able to remove the error
set_property IODELAY_GROUP selectio_adc_group [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch1_1/inst/idelaye2_bus]
set_property IODELAY_GROUP selectio_adc_group [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch1_1/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY2 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch1_2/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY2 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch1_2/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY3 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch2_1/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY3 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch2_1/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY4 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch2_2/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY4 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC1_ch2_2/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY5 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch1_1/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY5 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch1_1/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY6 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch1_2/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY6 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch1_2/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY7 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch2_1/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY7 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch2_1/inst/delayctrl]
set_property IODELAY_GROUP IO_DLY8 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch2_2/inst/idelaye2_bus]
set_property IODELAY_GROUP IO_DLY8 [get_cells ADC_FILES/Data_Capture_Clock_Process/ADC2_ch2_2/inst/delayctrl]
Can you let me know if i am right or not?
Thanks & Regards,