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Zoro100
Explorer
Explorer
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Registered: ‎05-22-2018

IODELAYE1 in 'VAR_LOADABLE' not giving the output on oscilloscope

Hello everyone,

 

I am trying to observe the phase shift between the clock input(C) and the DATAOUT using the primitive IODELAYE1 in 'VAR_LOADABLE' mode on virtex-6. One of the MMCM outputs is being fed as clock input(C) to the primitive. However when I dump the code on virtex-6, I cannot observe the DATAOUT at all(a flat response) which I am sure that the primitive is being given valid data. I have attached the code corresponding to the instantiations of primitives IODELAYE1 and IDELAYCTRL for reference.

Can someone tell me why is there no DATAOUT to observe and how to solve it?

 

Thanks in advance

 

-Chandrasekhar DVS

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8 Replies
kveerama
Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2019

Hi krishna,

The clock input should be given to the CLKIN port and the delay source should be CLKIN.

The port C (clock input of IODELAYE1) is dedicated for control inputs (INC,RST,CE) only.

Please have look on page 99 and 100 for port descriptions in UG361.

Capture1.PNG

Capture.PNG

Shall i know the reason for using IODELAYE1 to phaseshift the clock?

Thank you

Kind Regards,

Kasthuri

 

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Zoro100
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Registered: ‎05-22-2018

Hi @kveerama ,

 

The clock input(C) I am referring to, is the reference clock to increment the CNTVALUEIN when I am operating the IODELAYE1 primitive in VAR_LOADABLE mode. For testing purpose, I was giving a clock signal clk_25MHz to the DATAIN port which is the port I will actually be using later to feed valid data. Now, I think I must be able to atleast see this clk_25MHz signal with a delay coming out of DATAOUT port.

 

I am using the primitive to phase shift the data(which is a clock signal here; clk_25MHz) given at DATAIN port.

 

Is it so that if I want to use a clk signal as input and be able to observe the output, I HAVE to give the clk_25MHz to CLKIN, change the DELAY_SRC  to "CLKIN" and cannot use DATAIN in the way I did?

Can you please clarify?

Thanks in advance,

 

-Chandrasekhar DVS

 

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kveerama
Xilinx Employee
Xilinx Employee
1,144 Views
Registered: ‎05-07-2019

Hi ,

It seems like, you tied the ports CE and INC always to be ‘1’. Because of CE and INC tied to high the CNTVALUEIN will keep incrementing.

The below figure in UG361 will give you clear explanation for var_loadable mode. The CE and INC to be pulse more than it get tied  to 1 which makes more sense to increment the delay taps.

Capture3.PNG

 

Xilinx recommendation is to use

  1. CLKIN port for clock signal input from Clock Buffer
  2. DATAIN port for data signal input from FPGA Logic.
  3. ODATAIN port for data signal input from FPGA OLOGIC/OSERDES.
  4. IDATAIN port for Data input from IOB

Note: If you not use any of these ports then it should be tied off to Valid logic level ‘0’.

I have been noticed that you tied your CLKIN port to ‘Z’.

Try to redo the connections once again and simulate it to observe the results before implementing on Hardware.

Please have a look at the IODELAYE1 information in UG361.

Thank you

Kind Regards,

Kasthuri.

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Zoro100
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Registered: ‎05-22-2018

Hi @kveerama ,

 

With the exception of using DATAIN instead of IDATAIN, I can view the simulation output at DATOUT for the rest of the settings in the code I attached in my previous posts. However cannot observe the output on the oscilloscope.

 

Can you suggest why? Also specifically, is there a reason to tie CLKIN also to '0' instead of 'Z'?

 

Thanks in advance

 

-Chandrasekhar DVS

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kveerama
Xilinx Employee
Xilinx Employee
1,099 Views
Registered: ‎05-07-2019

Hi,

There is no tristate buffer inside the FPGA. If the CLKIN port is not used then it should be tied to valid logic level.

Might be in behavioural simulation you can observe the output for DATAOUT.

In Hardware, because CE and INC port is tied to high, it will continuously increment the CNTVALUEIN (like wrap around). Probably, that’s the reason for no output at DATAOUT when you are observing on the oscilloscope.

Have you tried the pulse signal for CE and INC instead of tied to high?

Have you used CLKIN port for clock input?

Thank you

Kind Regards,

Kasthuri.

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Zoro100
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Registered: ‎05-22-2018

Hi @kveerama,

 

Sorry for the late reply. Had to test the suggestions on hardware

As you suggested, I loaded an initial CNTVALUEIN and tied CLKIN and CE to '0'. Because INC does not matter now, I did not change the value of it.

Still no output.

I have also tried using CLKIN port as I am trying to observe clk alike signal. No output observed.

 

Can you suggest me how I can proceed?

 

Thanks in advance

 

 

-Chandrasekhar DVS

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kveerama
Xilinx Employee
Xilinx Employee
1,047 Views
Registered: ‎05-07-2019

Hi,

Hope you have tried with the below attributes,

DELAY_src=> "CLKIN"

CLKIN => clk_25MHz

CE => CE_PULSE

INC => INC_PULSE

If you are not observing any output at the pin on hardware still, then you may try to connect clock signal to the IO pin through ODDR without using IODELAYE1.

Check whether you get the clock signal at the pin.

Thank you

Kind Regards,

Kasthuri.

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Zoro100
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Explorer
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Registered: ‎05-22-2018

Hi @kveerama,

 

Sorry for the very late reply. However the problem has been solved when I used VARIABLE mode instead of VAR_LOADABLE mode. I was able to observe the required output.

 

Thank you for attending the question.

 

-Chandrasekhar DVS

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