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zaku89
Observer
Observer
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Registered: ‎05-30-2018

IP core to be accessd by ARM and MicroBlaze

Hi,

I am using ZYNQ7020 chips. We have 2 arms on PS side and 2 Microblaze on PL side.

We now want to realize the functions like:

The IP core generate some data and put it to a share memory which can be accessed by the first arm and both of the Microblaze. AXI bus solution is prefered.

 

Could anyone give some idea about this? Thank you!

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u4223374
Advisor
Advisor
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Registered: ‎04-26-2015

That should be fairly easy. AXI inherently supports multiple masters. Two easy options I can see:

(1) IP core has internal RAM, exposed as registers on an AXI Slave interface. Microblaze or the ARM cores can read/write those registers.

(2) IP core has an AXI Master which can then write data to a BRAM via an AXI BRAM controller, or to off-chip DDR via the Zynq HP AXI Slave ports. Microblaze and ARM can access that RAM to retrieve the results.

 

Xilinx provides examples of AXI Masters and AXI Slaves; have a look at those for more information.

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