That should be fairly easy. AXI inherently supports multiple masters. Two easy options I can see:
(1) IP core has internal RAM, exposed as registers on an AXI Slave interface. Microblaze or the ARM cores can read/write those registers.
(2) IP core has an AXI Master which can then write data to a BRAM via an AXI BRAM controller, or to off-chip DDR via the Zynq HP AXI Slave ports. Microblaze and ARM can access that RAM to retrieve the results.
Xilinx provides examples of AXI Masters and AXI Slaves; have a look at those for more information.