02-06-2019 12:11 PM
I'm using the CE1 pin on an ISERDES2 block that is configured in networking mode, with 1 CE. I have the signal that is controlling CE in the CLKDIV domain, but when I implement my design I get timing issues because it says it should be in the AdcBitClk domain. This seems odd to me because when I've looked at the documentation it claims:
If CE is being driven by a signal in CLKDIV why does it complain that it is supposed to be in the AdcBitClk domain?
02-06-2019 02:43 PM
Page 147-148 shows the detail of the clock enable here. It's really intended to be used as a 2:1 serial-to-parallel converter, clocked by CLKDIV.
The clock enable module is needed specifically for bidirectional memory interfaces when
ISERDESE2 is configured for 1:4 deserialization in DDR mode. When the attribute
NUM_CE = 2, the clock enable module is enabled and both CE1 and CE2 ports are
available. When NUM_CE = 1, only CE1 is available and functions as a regular clock enable.
Its the clock enable for the first rank of FFs in the iserdes so if num_ce is set to 1 by you then I could see how the tools expect it to be timed to the serial bit clock.
What is the purpose of this in your design?
02-06-2019 03:26 PM
It looks like that is the problem. I missed the fact that by setting NUM_CE to 1 it was bypassing the input registers and going straight into the ISERDES registers. By setting NUM_CE to 2 and tying both to the same enable line I was able to get rid of the timing issues.
My design is intended to recieve data from an ADC. Because I need to setup the ADC before I can align the SERDES link I needed to keep it disabled until the ADC is ready to send data.
02-07-2019 12:54 AM
Alternatively, you could hold the ISERDES in Reset until the ADC is ready to begin sending data.
If the deassertion of the reset is synchronous to CLKDIV then I would not forsee any issues.