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Explorer
Explorer
3,219 Views
Registered: ‎02-04-2013

ISERDES - MMCM Dynamic phase shift

Hello everybody,

 

I am using Artix7 and I would like to read data from serializer IC (FIN210AC in my case) using two LVDS signals only - without the clock from the serializer IC (please see the attached image). I thought i could dynamically shift the CKSI clock phase to match the DSO. Can this be done? 

 

So i should somehow limit the range of the phase shift to match the particular bit at ISERDES. Is this the way it should be done?

 

Regards

Klemen

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Moderator
Moderator
3,176 Views
Registered: ‎02-16-2010

If both FPGA and serializer are clocked using the same source, then you can adjust the phase of the clock driving the ISERDES of FPGA using IDELAY primitive.
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Explorer
Explorer
3,159 Views
Registered: ‎02-04-2013

The clock source is the same. The clock source generates strobe signal at the serializer.

 

Do you mean i should set it to fixed delay and experiment with the tap value or should i set it to dynamic - but in this case i will not know whether it was tuned to bit0 or not?

 

The strobe to bit0 delay is, for instance, at 20MHz: 77ns - 90,5ns. This is quite large compared to ps range delay for each tap.

 

Regards

Klemen

 

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