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Observer lasthorizon711
Observer
726 Views
Registered: ‎07-31-2018

ISERDES implementation on Spartan-7 device

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Hi all, 

 

I am implementing a design on a Spartan-7 device that requires a number of SERDES (There are 22 LVDS pairs). All the pins are placed on the same bank (in this case Bank 15 of an XC7S50FGGA484-2 device). An IDELAYE2 primitive is instantiated which the high speed clock is fed through to create a delayed clock. The delayed clock is fed into the relevant BUFIO and BUFR are primitives before being fed to the SERDES. 

 

When I try and implement this I get the following error: 

 

[Place 30-126] Unroutable Placement! A BUFIO can only drive loads in the same IO bank. The following BUFIO clock loads are placed too far from the BUFIO to be routable. 
	ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/clock_bufio (BUFIO.O) is provisionally placed by clockplacer on BUFIO_X0Y3
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[12].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y54
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[19].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y70
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[8].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y62
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[9].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y94
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[18].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y72
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[2].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y60
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[3].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y86
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[4].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y92
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[5].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y98
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[13].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y68
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[14].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y64
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[15].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y74
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[16].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y52
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[17].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y56
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[6].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y80
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[7].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKB) is locked to ILOGIC_X0Y96

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_iotile_bufr
	Status: FAIL 
	Rule Description: An IO driving a BUFR must both be placed in the same clock region
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_clock_delay.gen_delay_only.clock_delay (IDELAYE2.DATAOUT) is provisionally placed by clockplacer on IDELAY_X0Y28
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/clock_bufr (BUFR.I) is provisionally placed by clockplacer on BUFR_X0Y4
	ERROR: The above is also an illegal clock rule
	Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/adc_delayed_clk_se] >

	Clock Rule: rule_bufh_bufr_ramb
	Status: PASS 
	Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
	than the capacity of the region
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/clock_bufr (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y4

	Clock Rule: rule_bufr_IoClkLds
	Status: FAIL 
	Rule Description: A BUFR driving any number of IOBs must be placed within the same clock region
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/clock_bufr (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y4
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[12].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y54
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[19].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y70
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[19].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y70
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[8].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y62
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[8].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y62
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[9].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y94
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[9].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y94
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[0].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y82
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[0].blk_single_bit.serdes/gen_iodelay.data_n_delay (IDELAYE2.C) is locked to IDELAY_X0Y81
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[18].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y72
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[18].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y72
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[2].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y60
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[2].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y60
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[3].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y86
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[3].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y86
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[4].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y92
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[4].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y92
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[5].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y98
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[12].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y54
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[13].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y68
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[13].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y68
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[14].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y64
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[14].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y64
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[15].blk_single_bit.serdes/data_p_iserdes (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y74
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[15].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y74
	ERROR: The above is also an illegal clock rule
	Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/serdes_clk] >

	Clock Rule: rule_clk_locked_loads
	Status: PASS 
	Rule Description NOT AVAILABLE
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/clock_bufr (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y4
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[19].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y70
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[8].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y62
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[9].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y94
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[0].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y82
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[0].blk_single_bit.serdes/gen_iodelay.data_n_delay (IDELAYE2.C) is locked to IDELAY_X0Y81
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[18].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y72
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[2].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y60
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[3].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y86
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[4].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y92
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[12].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y54
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[13].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y68
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[14].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y64
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[15].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y74
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[16].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y52
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[17].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y56
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[5].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y98
	 ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[6].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y80
	 and ADC_if/gen_adc_data_capture[0].adc_data_capture0/adc_lvds_capture0/gen_single_bit[7].blk_single_bit.serdes/gen_iodelay.data_p_delay (IDELAYE2.C) is locked to IDELAY_X0Y96

As far as I can tell from reading the SelectIO and Clocking Resources documents, the BUFIO and BUFR should be capable of driving resources across the entire bank. However, the error message implies it is using BUFR and BUFIO resources from a different bank, therefore the fan out can't complete. 

 

Ideas?

 

Thanks 

Alex 

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Observer lasthorizon711
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675 Views
Registered: ‎07-31-2018

Re: ISERDES implementation on Spartan-7 device

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I think I have worked it out. The design I was given for the SERDES implementation appeared to be building individual clock buffers for every SERDES. I have now re-written the design and the place and route process passes. 

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Moderator
Moderator
700 Views
Registered: ‎04-18-2011

Re: ISERDES implementation on Spartan-7 device

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I think you should do synthetic design with no location constraints. Then open the post synth netlist and apply the placement. Then run a DRC.
Another step is Look at the bufio/bufr sites it is calling out in these error message and check are they in the clock region for bank 15.
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Observer lasthorizon711
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Registered: ‎07-31-2018

Re: ISERDES implementation on Spartan-7 device

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I think I have worked it out. The design I was given for the SERDES implementation appeared to be building individual clock buffers for every SERDES. I have now re-written the design and the place and route process passes. 

View solution in original post

Moderator
Moderator
673 Views
Registered: ‎04-18-2011

Re: ISERDES implementation on Spartan-7 device

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Thanks for the update. I hope the steps I suggested helped. 

 

Have a good weekend. 

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