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Observer daveb1
Observer
1,020 Views
Registered: ‎04-08-2016

ISERDES with delay issue

Hi,

 

This is a follow-up to a question about IODELAY2 with more detail in case someone can help.

 

I have a 4-bit word clocked by a DDR clock, all of which connect to device pins. I want to delay the clock to meet set-up time. I used the ISE SelectIO wizard to generate a ISERDES with a variable input delay but I get an error saying that the two BUFIO2s that get generated can't be routed due to pin constraints (the SERDES routes fine without the delays inserted).

 

I can't change the pin assignments so I removed the delays from the SelectIO wizard and 'manually' added delays. I've inserted fixed IODELAY2's between the data pins and SERDES data inputs then a variable IODELAY2 between the clock pin and the SERDES clock input. On the IODELAY2 components I've connected the pins and their delayed versions to IDATAIN and DATAOUT respectively which seems reasonable. However I get the following:

 

ERROR:NgdBuild:455 - logical net 'DataIn_Delayed(x)' has multiple driver(s):
     pin DATAOUT on block IODELAY2_DataIn(x) with type IODELAY2,
     pin PAD on block DataIn_Delayed(x) with type PAD

 

Is it legal to insert delays between device pins and a ISERDES, and if so, any idea why I get the above error ?

 

Thanks

Dave

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4 Replies
Scholar drjohnsmith
Scholar
983 Views
Registered: ‎07-09-2009

Re: ISERDES with delay issue

we need to know your device and the code your using 

 

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Observer daveb1
Observer
946 Views
Registered: ‎04-08-2016

Re: ISERDES with delay issue

Hi drjohnsmith,

 

The device I'm using is a Spartan6 LX9 and the code I'm using to instantiate the delays between the clock & data lines on the device pins and ISERDES is:

 

Variable delay on the clock

=====================
   IODELAY2_DataInClk : IODELAY2
   generic map (
      COUNTER_WRAPAROUND => "STAY_AT_LIMIT",     -- "STAY_AT_LIMIT" or "WRAPAROUND"
      DATA_RATE => "SDR",                         -- "SDR" or "DDR"
      DELAY_src=> "IDATAIN",                     -- "IO", "ODATAIN" or "IDATAIN"
      IDELAY_TYPE => "VARIABLE_FROM_ZERO",        -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
      IDELAY_VALUE => 0,                          -- Amount of taps for fixed input delay (0-255)
      ODELAY_VALUE => 0,                         -- Amount of taps fixed output delay (0-255)
      SERDES_MODE => "NONE",                      -- "NONE", "MASTER" or "SLAVE"
   )
   port map (
      BUSY => open,                     -- 1-bit output: Busy output after CAL
      DATAOUT => DataInClk_Delayed,      -- 1-bit output: Delayed data output to ISERDES/input register
      DATAOUT2 => open,                 -- 1-bit output: Delayed data output to general FPGA fabric
      DOUT => open,                     -- 1-bit output: Delayed data output
      TOUT => open,                     -- 1-bit output: Delayed 3-state output
      CAL => '0',                       -- 1-bit input: Initiate calibration input
      CE => Delay_enable,                -- 1-bit input: Enable INC input
      CLK => Sysclk,                       -- 1-bit input: Clock input
      IDATAIN => InDataClk,              -- 1-bit input: Data input (connect to top-level port or I/O buffer)
      INC => Delay_incdec,                 -- 1-bit input: Increment / decrement input
      IOCLK0 => '0',                     -- 1-bit input: Input from the I/O clock network
      IOCLK1 => '0',                     -- 1-bit input: Input from the I/O clock network
      ODATAIN => '0',                       -- 1-bit input: Output data input from output register or OSERDES2.
      RST => Delay_reset,                  -- 1-bit input: Reset to zero or 1/2 of total delay period
      T => '1'                           -- 1-bit input: 3-state input signal
   );

 

Fixed delays on D0:D3

==================

   IODELAY2_DataIn0 : IODELAY2
   generic map (
      COUNTER_WRAPAROUND => "STAY_AT_LIMIT",     -- "STAY_AT_LIMIT" or "WRAPAROUND"
      DATA_RATE => "SDR",                         -- "SDR" or "DDR"
      DELAY_src=> "IDATAIN",                     -- "IO", "ODATAIN" or "IDATAIN"
      IDELAY2_VALUE => 0,                         -- Delay value when IDELAY_MODE="PCI" (0-255)
      IDELAY_MODE => "NORMAL",                    -- "NORMAL" or "PCI"
      IDELAY_TYPE => "FIXED",                    -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
      IDELAY_VALUE => 128,                      -- Amount of taps for fixed input delay (0-255)
      ODELAY_VALUE => 0,                         -- Amount of taps fixed output delay (0-255)
      SERDES_MODE => "NONE",                      -- "NONE", "MASTER" or "SLAVE"
   )
   port map (
      BUSY => open,                     -- 1-bit output: Busy output after CAL
      DATAOUT => DataIn_Delayed(0),     -- 1-bit output: Delayed data output to ISERDES/input register
      DATAOUT2 => open,                 -- 1-bit output: Delayed data output to general FPGA fabric
      DOUT => open,                     -- 1-bit output: Delayed data output
      TOUT => open,                     -- 1-bit output: Delayed 3-state output
      CAL => '0',                       -- 1-bit input: Initiate calibration input
      CE => Delay_enable,                -- 1-bit input: Enable INC input
      CLK => Sysclk,                       -- 1-bit input: Clock input
      IDATAIN => DataIn(0),              -- 1-bit input: Data input (connect to top-level port or I/O buffer)
      INC => Delay_incdec,                 -- 1-bit input: Increment / decrement input
      IOCLK0 => '0',                     -- 1-bit input: Input from the I/O clock network
      IOCLK1 => '0',                     -- 1-bit input: Input from the I/O clock network
      ODATAIN => '0',                       -- 1-bit input: Output data input from output register or OSERDES2.
      RST => Delay_reset,                  -- 1-bit input: Reset to zero or 1/2 of total delay period
      T => '1'                           -- 1-bit input: 3-state input signal
   );

 

Just to re-iterate, the errors I get for all 5 instantiations is:

 

ERROR:NgdBuild:455 - logical net 'DataIn_Delayed(x)' has multiple driver(s):
     pin DATAOUT on block IODELAY2_DataIn(x) with type IODELAY2,
     pin PAD on block DataIn_Delayed(x) with type PAD

 

Is it legal to insert delays between device pins and a ISERDES, and if so, any idea why I get the above error ?

 

Thanks

Dave

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Scholar drjohnsmith
Scholar
938 Views
Registered: ‎07-09-2009

Re: ISERDES with delay issue

The code snippet does not tell us much

   I was more thinking how have you connected the blocks,

       can you attach your code ?

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer daveb1
Observer
920 Views
Registered: ‎04-08-2016

Re: ISERDES with delay issue

I've realised what the problem is.

 

I am using a SERDES generated using the SelectIO wizard and looking at the generated VHDL it puts IBUFs in the clock and data paths between the device pins and the SERDES. Manually adding an IODELAY2 causes the SERDES input to be driven from multiple sources. Replacing the IBUFs with IODELAY2 now synthesises. After looking at the various documented IODELAY2 issues I think I might switch to a Spartan7 which appears to have a much more stable IODELAY2 implementation.

 

Thanks for your input.

 

Dave

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