after simulating a module using ISERDESE2 and IDELAYE2 countless times, clocked by a MMCM with clock phases according to AR# 57966, I finally tried to reverse the phase shift between CLK and CLKDIV. This caused the deserializer to work correctly immediately, while I previously had the two-bit shift as described in the mentioned AR.
Also, Tables 33 and 34 in DS181, which list the propagation delays for BUFR and BUFIO, show that any signal applied to both the BUFIO and BUFR appears at the output of BUFR 500 ps earlier than at the output of the BUFIO.
While I'm not entirely sure, I have to come to the conclusion that the entire AR# 57966 is "swapped" regarding CLK and CLKDIV and their timing relationship.
Can somebody please check this and also correct the AR if this is in fact the case?